Resource-Aware Task Scheduling and Placement in Multi-FPGA System

Abstract

With the development of high performance computing, Field Programmable Gate Arrays (FPGAs) are widely used for task acceleration. Partial reconfigurable technology provides the possibility of multi-task concurrent computation on FPGAs. However, it is still difficult to achieve high performance multi-task acceleration in multi-FPGA systems due to the resource contention in limited hardware resources and reconfiguration overhead. In this paper, we propose a two-stage task scheduling approach in multi-FPGA systems to optimize task execution efficiency. At the first scheduling stage, we select an appropriate computing unit for each task considering the subtask similarity and resource requirement similarity to reduce the possibility of reconfiguration and resource contention. At the second scheduling stage, we coordinate the subtask scheduling and placement to make full use of the hardware resources of FPGAs and improve the acceleration performance. Experiments show that our two-stage scheduling approach significantly reduces the tasks makespan and improves the utilization of resources compared with other traditional methods. INDEX TERMS Multi-FPGA, task scheduling, task placement, partial reconfiguration.

Desafios para a Computação Energeticamente Eficiente

“…Essas simplificações podem levar a soluções teóricas ineficientes ou que não são implementáveis na prática devido às restrições geométricas do dispositivo que devem ser respeitadas [AMD 2023b]. Em [Sun et al 2019] é apresentado um algoritmo para o posicionamento de tarefas em múltiplos FPGAs que modela os recursos heterogêneos e as restrições geométricas de particionamento, entretanto desconsiderando o possível caráter distribuído desses dispositivos, que pode introduzir restrições de latência e banda para as soluções.…”

Resource Partitioning and Application Scheduling with Module Merging on Dynamically and Partially Reconfigurable FPGAs

“…Ref. [19] proposes a two-stage task scheduling approach in multi-FPGA systems to optimize task execution efficiency. Ref.…”