A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops

Natale, Giuseppe; Stramondo, Giulio; Bressana, Pietro; Cattaneo, Riccardo; Sciuto, D.; Santambrogio, Marco D.

doi:10.1145/2966986.2966995

Cited by 25 publications

(19 citation statements)

References 15 publications

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“…Deest et al [9] propose an HLS-based code-generator that generates accelerators that are architecturally similar to CA. Similarily, Natale et al [31] propose an accelerator generation approach for SST. In addition, DSLs such as Halide [38] and Delite [50] are applicable to ISLs.…”

Section: Domain Specific Languages and Code-generators For Islsmentioning

confidence: 96%

Dcmi

Koraei

Fatemi

Jahre

2019

ACM Trans. Archit. Code Optim.

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Iterative Stencil Loops (ISLs) are the key kernel within a range of compute-intensive applications. To accelerate ISLs with Field Programmable Gate Arrays, it is critical to exploit parallelism (1) among elements within the same iteration and (2) across loop iterations. We propose a novel ISL acceleration scheme called Direct Computation of Multiple Iterations (DCMI) that improves upon prior work by pre-computing the effective stencil coefficients after a number of iterations at design time-resulting in accelerators that use minimal on-chip memory and avoid redundant computation. This enables DCMI to improve throughput by up to 7.7× compared to the state-of-the-art cone-based architecture. CCS Concepts: • Computer systems organization → Architectures; • Computing methodologies → Parallel computing methodologies;

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Section: Domain Specific Languages and Code-generators For Islsmentioning

confidence: 96%

Dcmi

Koraei

Fatemi

Jahre

2019

ACM Trans. Archit. Code Optim.

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“…The basic structure of ISLs is depicted in Algorithm 8.1; the outer loop iterates for a given number of times, so-called time-steps, while, at each time-step, the inner The Streaming architectural template specifically targets stencil codes written in C and leverages the SST architecture proposed by [3] for its implementation. The architectural template of the SST-based accelerator [14] is depicted in Fig. 8.3.…”

Section: Streaming Architectural Templatementioning

confidence: 99%

CAOS: CAD as an Adaptive Open-Platform Service for High Performance Reconfigurable Systems

Rabozzi

2019

Special Topics in Information Technology

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The increasing demand for computing power in fields such as genomics, image processing and machine learning is pushing towards hardware specialization and heterogeneous systems in order to keep up with the required performance level at sustainable power consumption. Among the available solutions, Field Programmable Gate Arrays (FPGAs), thanks to their advancements, currently represent a very promising candidate, offering a compelling trade-off between efficiency and flexibility. Despite the potential benefits of reconfigurable hardware, one of the main limiting factor to the widespread adoption of FPGAs is complexity in programmability, as well as the effort required to port software solutions to efficient hardware-software implementations. In this chapter, we present CAD as an Adaptive Open-platform Service (CAOS), a platform to guide the application developer in the implementation of efficient hardware-software solutions for high performance reconfigurable systems. The platform assists the designer from the high-level analysis of the code, towards the optimization and implementation of the functionalities to be accelerated on the reconfigurable nodes. Finally, CAOS is designed to facilitate the integration of external contributions and to foster research on Computer Aided Design (CAD) tools for accelerating software applications on FPGA-based systems.

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“…Approach vs. characteritics non-tiled on-chip [6] non-tiled off-chip [5], [9] partial oblique tiling [10] full oblique tiling (ours) overlapped tiling [7] Domain size scalability…”

Section: B Overview Of the Execution Datapathmentioning

confidence: 99%

“…Partial tiling [10] is an attractive alternative for small problem sizes. We implemented this strategy and compared to fully tiled cases.…”

Section: Comparison With Earlier Workmentioning

confidence: 99%

One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs

Deest

Yuki²,

Rajopadhye³

et al. 2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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We generate a family of FPGA stencil accelerators targeting emerging System on Chip platforms, (e.g., Xilinx Zynq or Intel SoC). Our designs come with design knobs to explore trade-offs. We also propose performance models to hone in on the most interesting design points, and show how they accurately lead to optimal designs. The optimal choice depends on problem sizes and performance goals. I. INTRODUCTIONIterative stencil computations arise in many application domains, ranging from medical imaging to numerical simulation. Since they are computationally demanding, a large body of work addressed the problem of parallelizing and optimizing stencils for multi-cores, GPUs, and FPGAs.Earlier attempts targeting FPGAs showed that the performance of such accelerators is a complex interplay between the raw FPGA computing power, the amount of on-chip memory, and the performance of the external memory system [1]- [8]. They also illustrate different application requirements. For example, in the context of embedded vision, designers often seek the cheapest design achieving real-time performance constraints (e.g., 4K@60fps). In an exascale context, they may want to maximize performance (measured in ops-persecond) for a given FPGA board, while maintaining power dissipation to a minimum. Therefore, we explore a family of design options that can accommodate a large set of constraints, by exposing trade-offs between computing power, bandwidth requirements, and FPGA resource usage. We focus on system-level issues. Our aim is not to provide hand-optimized FPGA implementations. We have developed a code generator that produces HLS-optimized C/C++ descriptions of accelerator instances, leaving low-level decisions to the HLS back-end.Our designs build upon the tiling transformation, that we use to balance on-chip memory cost and off-chip bandwidth. The design space we explore can be characterized by the following design knobs.

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A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops

Cited by 25 publications

References 15 publications

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CAOS: CAD as an Adaptive Open-Platform Service for High Performance Reconfigurable Systems

One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs

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