On How to Accelerate Iterative Stencil Loops

Abstract

In high-performance systems, stencil computations play a crucial role as they appear in a variety of different fields of application, ranging from partial differential equation solving, to computer simulation of particles' interaction, to image processing and computer vision. The computationally intensive nature of those algorithms created the need for solutions to efficiently implement them in order to save both execution time and energy. This, in combination with their regular structure, has justified their widespread study and the proposal of largely different approaches to their optimization. However, most of these works are focused on aggressive compile time optimization, cache locality optimization, and parallelism extraction for the multicore/multiprocessor domain, while fewer works are focused on the exploitation of custom architectures to further exploit the regular structure of Iterative Stencil Loops (ISLs), specifically with the goal of improving power efficiency. This work introduces a methodology to systematically design power-efficient hardware accelerators for the optimal execution of ISL algorithms on Field-programmable Gate Arrays (FPGAs). As part of the methodology, we introduce the notion of Streaming Stencil Time-step (SST), a streaming-based architecture capable of achieving both low resource usage and efficient data reuse thanks to an optimal data buffering strategy, and we introduce a technique called SSTs queuing that is capable of delivering a pseudolinear execution time speedup with constant bandwidth. The methodology has been validated on significant benchmarks on a Virtex-7 FPGA using the Xilinx Vivado suite. Results demonstrate how the efficient usage of the on-chip memory resources realized by an SST allows one to treat problem sizes whose implementation would otherwise not be possible via direct synthesis of the original, unmanipulated code via High-Level Synthesis (HLS). We also show how the SSTs queuing effectively ensures a pseudolinear throughput speedup while consuming constant off-chip bandwidth. CCS Concepts: r Hardware → Hardware-software codesign; Methodologies for EDA; Sequential circuits; r Software and its engineering → Data flow architectures; r Theory of computation → Streaming models; Massively parallel algorithms;

Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL

“…Previous work [1,9,20,22] have shown that FPGAs can achieve GPU-level performance in stencil computation. Most of such work achieve this level of performance by relying on temporal blocking without spatial blocking.…”

Dcmi

“…In this section, we provide an example that illustrates why the DCMI acceleration strategy is superior to current state-of-the-art FPGA-based accelerators [4,40]. We first explain the operation of the stencil compute kernel in Section 2.1.…”

“…The importance and high potential for parallelism makes ISL-applications an interesting acceleration target. However, developing efficient ISL accelerators is challenging for two reasons [4]. First, ISL-applications operate on a large data array in which all data elements are typically updated in each iteration of the outer-loop.…”

“…However, there are only two main architectural approaches for implementing accelerators that exploit both spatial and temporal parallelism. The first approach is exemplified by the Streaming Stencil Time-step (SST) [4] scheme. SST is memory centric and streams the data array through the FPGA while performing the stencil computation.…”

Extra

“…CAOS currently supports three different architectural templates: SST (Single Stencil Time-Step), Master-Slave, and Dataflow. SST provides an architecture targeted for stencil codes written in C [21]. Within this context, CAOS offers a design exploration algorithm [22] that jointly maximizes the number of SST processors that can be instantiated on the target FPGA, and identifies a floorplan of the design that minimizes the inter-component wire-length in order to allow implementing the system at a higher frequency.…”