Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCL

Abstract

Recent developments in High Level Synthesis tools have attracted software programmers to accelerate their high-performance computing applications on FPGAs. Even though it has been shown that FPGAs can compete with GPUs in terms of performance for stencil computation, most previous work achieve this by avoiding spatial blocking and restricting input dimensions relative to FPGA on-chip memory. In this work we create a stencil accelerator using Intel FPGA SDK for OpenCL that achieves high performance without having such restrictions. We combine spatial and temporal blocking to avoid input size restrictions, and employ multiple FPGA-specific optimizations to tackle issues arisen from the added design complexity. Accelerator parameter tuning is guided by our performance model, which we also use to project performance for the upcoming Intel Stratix 10 devices. On an Arria 10 GX 1150 device, our accelerator can reach up to 760 and 375 GFLOP/s of compute performance, for 2D and 3D stencils, respectively, which rivals the performance of a highly-optimized GPU implementation. Furthermore, we estimate that the upcoming Stratix 10 devices can achieve a performance of up to 3.5 TFLOP/s and 1.6 TFLOP/s for 2D and 3D stencil computation, respectively. CCS CONCEPTS• Hardware → Reconfigurable logic and FPGAs; High-level and register-transfer level synthesis;

High-Performance High-Order Stencil Computation on FPGAs Using OpenCL

“…• Loop collapsing to reduce area overhead of storing variable and buffer states in multiply-nested loops • Padding relative to the degree of temporal parallelism to reduce unaligned accesses caused by overlapped blocking that result in memory bandwidth waste Complete details of our implementation and the performance model we use for parameter tuning are discussed in [8].…”

“…To extend out base implementation from [8] for high-order stencil computation, multiple modifications were required:…”

“…Since stencil radius had already been considered in our performance model in [8], no further changes were required in the model to support high-order stencils.…”

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

“…Recently, a stencil accelerator using Intel OpenCL was presented in the work of Zohouri et al, where the authors highlight two important concerns about the compiler. First, due the Partial Reconfiguration on Arria 10 FPGAs, the fitting and routing quality for OpenCL is reduced on Arria 10.…”

“…One way is to focus on application and domain‐specific accelerators: Neural network, Bayesian learning, bioinformatics, stencil computing, energy‐efficient accelerators for graph analytics algorithms, and irregular applications mapping . Another way is to focus on Domain‐Specific Language (DSL) which aims representing parallelism in stream‐based applications, like SPar based on C++ …”