ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

Abstract

Summary Dataflow‐based FPGA accelerators have become a promising alternative to deliver energy‐efficient high‐performance computing. However, FPGA programming is still a challenge. This paper presents Accelerator Design and Deploy (ADD), a high‐level framework to specify, to simulate, and to implement dataflow accelerators for streaming applications. The framework includes an open dataflow operator library, and templates are provided to easily design new operators. The framework also provides a high‐level and an accurate simulation at circuit level with short execution times. Moreover, ADD provides software and hardware APIs to simplify the integration process, extending the benefits of portability from low‐cost FPGA boards to high performance datacenter FPGA platforms. Our framework supports coupling with high‐level programming languages, and it has been validated on two FPGA platforms: the Intel high‐performance CPU‐FPGA heterogeneous computing platform and an educational FPGA kit. We show that our simple approach presents competitive performance, both in time and energy, when compared to multi‐core and GPU accelerators.

Google Colab CAD4U: Hands-On Cloud Laboratories for Digital Design

“…Finally, our outcome results in an all-in-one intuitive and flexible browser-based cloud framework to learn computer architecture and CAD design techniques and tools by interactive examples embedded in an incremental graphical/text browser interface. In future work, we will evaluate open source [24] and cloud computing by using FPGAs [25], [26].…”

Plain: Ferramenta para Desenvolvimento de Aceleradores para Overlays em FPGA na Nuvem em Tempo de Execução

“…A Tabela 3 resume a comparação com outras ferramentas e abordagens para desenvolvimento de aceleradores. A coluna Comp exige a ordem de grandeza para compilação, Primeiro, a ferramenta ADD [Penha et al 2019] permite a descrição de grafos de forma explícita, porém gera um código Verilog que deve ser sintetizada, que pode demorar horas, para ser depois implementado no FPGA. O compilador CCF [Dave and Shrivastava 2017] não requer síntese, extraí o grafo de um código C/C++, porém requer minutos para compilar e não foi validado em FPGA.…”

“…O custo de projetos em ASIC (circuitos dedicados)é elevado para mapeamento dos grafos de fluxo. Uma alternativaé o uso de hardware reconfigurável como os FP-GAs [Penha et al 2019]. Porém, o desenvolvimento com FPGA ainda exige um conhecimento detalhado do hardware e de uma linguagem de descrição de hardware, normalmente Verilog ou VHDL.…”

Foreword to the special issue of the workshop on high performance computing systems (XVIII Simpósio em Sistemas Computacionais de Alto Desempenho, WSCAD 2017)

“…In this context, the paper “ ADD: Accelerator Design and Deploy ‐ A Tool for FPGA High Performance Dataflow Computing ” presents a high‐level framework to specify, to simulate, and to implement dataflow accelerators for streaming applications . The Accelerator Design and Deploy (ADD) framework includes an open dataflow operator library, and templates are provided to easily design new operators.…”