High-Performance High-Order Stencil Computation on FPGAs Using OpenCL

Abstract

In this paper we evaluate the performance of FPGAs for high-order stencil computation using High-Level Synthesis. We show that despite the higher computation intensity and onchip memory requirement of such stencils compared to first-order ones, our design technique with combined spatial and temporal blocking remains effective. This allows us to reach similar, or even higher, compute performance compared to first-order stencils. We use an OpenCL-based design that, apart from parameterizing performance knobs, also parameterizes the stencil radius. Furthermore, we show that our performance model exhibits the same accuracy as first-order stencils in predicting the performance of high-order ones. On an Intel Arria 10 GX 1150 device, for 2D and 3D star-shaped stencils, we achieve over 700 and 270 GFLOP/s of compute performance, respectively, up to a stencil radius of four. These results outperform the state-of-theart YASK framework on a modern Xeon for 2D and 3D stencils, and outperform a modern Xeon Phi for 2D stencils, while achieving competitive performance in 3D. Furthermore, our FPGA design achieves better power efficiency in almost all cases.

AN5D: automated stencil framework for high-degree temporal blocking on GPUs

“…Similarly, 1.5D spatial blocking can be used for 2D stencils. This blocking technique has been widely employed on different devices [17,23,40,41], with not just two, but also more combined time-steps. In 2.5D spatial blocking, the 2D tiles are streamed over one dimension and data of each tile is effectively reused for updating the next tiles.…”

“…LIFT [11] is a functional data-parallel programming language that allows expressing stencil loops as a set of reusable parallel primitives and optimizing them. Recently, multiple implementations of N.5D blocking on FPGAs have also been proposed with FPGA-specific optimizations [4,5,40,41]. FPGAs tend to achieve better scaling with temporal blocking compared to GPUs due to higher flexibility of employing their on-chip memory which allows larger spatial block sizes compared to GPUs.…”

The Memory Controller Wall: Benchmarking the Intel FPGA SDK for OpenCL Memory Interface

“…A halo size of zero results in simple sequential reading/writing with no overlapping. The second and third classes implement 1.5D and 2.5D overlapped spatial blocking, respectively, that are widely used in 2D and 3D stencil computation [5,6,7,8,9,10]. For the 1.5D class, the x dimension is blocked and memory accesses are streamed row by row until the last index in the y dimension, before moving to the next block ( Fig.…”

“…The 1.5D and 2.5D blocking classes support all the above array configurations except R1W0. All Single Work-item kernels use collapsed loops with the exit condition optimization from [4,5,6] for best timing and hence, are constructed as a doubly-nested loops, with the fully-unrolled innermost loop having a trip count equal to the vector size, and the outer loop having an initiation interval of one. In the NDRange kernels, the workgroups have the same number of dimensions as the input, and memory access coalescing is performed using loop unrolling.…”

“…It has been shown that due to the low external memory bandwidth and low byte to FLOP ratio of modern FPGAs, it is frequently not possible to fully utilize the compute performance of these devices for typical applications [1,4]. Moreover, even this limited external memory bandwidth cannot always be efficiently utilized due to limitations in the memory controller [4,5,6]. In this work, we will focus on analyzing the efficiency of the external memory controller on Intel FPGAs for OpenCL-based designs under different configurations.…”