Nanocomposites that contain reinforcements with preferred orientation have attracted significant attention because of their promising applications in a wide range of multifunctional fields. Many efforts have recently been focused on developing facile methods for preparing aligned graphene sheets in solvents and polymers because of their fascinating properties including liquid crystallinity and highly anisotropic characteristics. Self-aligned in situ reduced graphene oxide (rGO)/polymer nanocomposites are prepared using an all aqueous casting method. A remarkably low percolation threshold of 0.12 vol% is achieved in the rGO/epoxy system owing to the uniformly dispersed, monolayer graphene sheets with extremely high aspect ratios (>30000). The self-alignment into a layered structure at above a critical filler content induces a unique anisotropy in electrical and mechanical properties due to the preferential formation of conductive and reinforcing networks along the alignment direction. Accompanied by the anisotropic electrical conductivities are exceptionally high dielectric constants of over 14000 with 3 wt% of rGO at 1 kHz due to the charge accumulation at the highly-aligned conductive filler/insulating polymer interface according to the Maxwell-Wagner-Sillars polarization principle. The highly dielectric rGO/epoxy nanocomposites with the engineered structure and properties present high performance electromagnetic interference shielding with a remarkable shilding efficiency of 38 dB.

Self‐driven photodetectors have wide applications in wireless sensor networks and wearable physiological monitoring systems. While 2D materials have different bandgaps for potential novel application fields, the self‐driven photodetectors are mainly built on PN junctions or heterostructures, whose fabrication involves doping or reliable multiple transfer steps. In this study, a novel metal–semiconductor–metal (MSM) WSe2 photodetector with asymmetric contact geometries is proposed. A high responsivity of 2.31 A W−1 is obtained under zero bias, and a large open‐circuit voltage of 0.42 V is achieved for an MSM photodetector with a large contact length difference. The MSM photodetector can overcome the disadvantage of high dark current in traditional MSM photodetectors. A small dark current of ≈1 fA along with a high detectivity of 9.16 × 1011 Jones is achieved. The working principles and finite element analysis are presented to explain the origin of the self‐driven property and its dependence on the degree of asymmetry.

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A system-on-chip passive UHF RFID tag with embedded temperature sensor is developed in a standard 0.18µm CMOS process for the EPC Gen-2 protocol from 860-960MHz [1]. Flip-chip technology is used to bond the developed tag IC to an antenna to realize a complete tag inlay, which is successfully demonstrated and evaluated in real-time wireless communications with commercial RFID readers. Figure 17.1.1 shows the block diagram of the tag IC. Multiple supply voltages, generated by a power management unit (PMU) using a separate-storage-capacitor technique to save area, are employed to optimize the performance of individual building blocks, while minimizing the total power consumption. A dualpath clock generator is used to generate on-chip clocks for signal processing to support both applications with either very accurate link frequency or very low power consumption. A low-power temperature sensor is also embedded with a gain-compensation technique that makes use of current correlation from the same bandgap reference (BGR) for the clock generator to reduce the temperature sensing error due to process variations.Figure 17.1.2 shows the PMU. The rectifier (RECT1) supplies the 670nA BGR while the core RF-DC conversion is performed by a triple-output rectifier (RECT2). Further supply regulation is done using low-dropout regulators (LDRs). For the duration of PW (=Tari/2) [1], as the RF input is significantly attenuated due to the data modulation, the rectifier becomes inactive, and a storage capacitor C S is employed to supply both the load current I L and the reverse leakage current I leak that flows back to the rectifier, which results in a ripple voltage of VR CS =(I L +I leak )×PW/C S . In existing work [2], all the blocks share one single capacitor C S , which needs to be large enough to meet the ripple voltage requirement of the most noise-sensitive block. To provide a highly stable current for the dual-path clock generator, the BGR is required to have a small supply ripple of 0.1V, and, as a result, the single C S would need to be at least 1.75nF to supply the nominal total I L of 14µA when Tari=25µs. In our work, three separate capacitors, C Sx (x=1,2,3), are employed for different blocks with different optimal ripple voltages (0.4V, 0.25V, 0.1V, respectively), which helps to significantly reduce the total capacitance to 805pF, even with >10% margins. The switches S x (x=1,2,3) are controlled by the demodulator's output to cut off I leak during PW, which helps further reduce both the sizes of C Sx and the required input power for replenishing. M ST1 and M ST2 are used for start-up. High voltages of 3.5V and 7.8V, used for programming the OTP memory, are generated by three charge pumps (QPs). During the WRITE operation, a VCO is activated to regulate the QP_VPP's output at 7.8V with an output current up to 20µA. With sufficient input power, the power detector (PD) sends a Power-Good (PG) signal to turn on S 4 to power up LDR 3 for the injection-locked frequency divider (ILFD) in the dual-path clock generator. Figure 17...

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High performance super TFT's with different channel widths and lengths, formed by a novel grain enhancement method, are reported. High temperature annealing has been utilized to enhance the polysilicon grain and improve the quality of silicon crystal after low temperature MILC treatment on amorphous silicon. With device scaling, it is possible to fabricate the entire transistor on a single grain, thus giving the performance of single crystal SOI MOSFET. The effects of grain boundaries on device performance have been studied, indicating the existence of extra leakage current paths caused by the grain boundaries traversing the channel, which induced subthreshold hump and early punchthrough of wide devices. The probability for the channel region of a TFT to cover multiple grains decrease significantly when the device is scaled down, resulting in better device performance and higher uniformity.