Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method

Abstract

High performance super TFT's with different channel widths and lengths, formed by a novel grain enhancement method, are reported. High temperature annealing has been utilized to enhance the polysilicon grain and improve the quality of silicon crystal after low temperature MILC treatment on amorphous silicon. With device scaling, it is possible to fabricate the entire transistor on a single grain, thus giving the performance of single crystal SOI MOSFET. The effects of grain boundaries on device performance have been studied, indicating the existence of extra leakage current paths caused by the grain boundaries traversing the channel, which induced subthreshold hump and early punchthrough of wide devices. The probability for the channel region of a TFT to cover multiple grains decrease significantly when the device is scaled down, resulting in better device performance and higher uniformity.

In situ observation of nickel metal-induced lateral crystallization of amorphous silicon thin films

“…7,8 The conventional solid phase crystallization ͑SPC͒ process spends several dozen hours at around 600°C to obtain defect-rich polysilicon films; 9 by contrast the Ni-MILC process occurs at lower temperatures, ranging from 450 to 550°C, and gives larger crystalline grains with improved electrical characteristics. 7 It is also reported that polysilicon TFTs fabricated by the combination of Ni-MILC process and subsequent annealing at 900°C for 30 min exhibit high electron mobility of 430 cm 2 V Ϫ1 s Ϫ1 .…”

Self-aligned offset gate poly-Si TFTs using photoresist trimming technology

“…They were acting as buried oxide, active layer and sacrificial oxide, respectively. In this work, the metal-induced lateral crystallization (MILC) technology with nickel as catalyst was used to recrystallize the amorphous silicon film to poly-Si film at low temperature [11], as shown in Figure 1(a). The inducing windows for the MILC process were opened on the sacrificial LTO layer using conventional photolithography and wet etch.…”

Influence of annealing temperature and Au concentration on the electrical properties of multilayered a-Ge/Au films

“…However, this process is required with high-temperature (~723 K) annealing. In SPC process, Si ion implantation [7] and deposition of metal on the a-Si [8] are increasing the crystal nucleation in the film. Metal-induced crystallization (MIC) technique, that is one of SPC method, is a method for obtaining polycrystalline of large grain size at extremely lowtemperature on insulating substrate [9].…”