An Analytical Charge Model for Double-Gate Tunnel FETs

Universal analytic model for tunnel FET circuit simulation

“…Quite a few compact analytic models for the TFET have been developed [4][5][6][7][8][9][10][11][12][13][14]. Refs.…”

“…Refs. [4][5][6][7][8][9] employ a semianalytical solution of Poisson's equation in the channel region to model the channel charge [4] or to obtain the current-voltage characteristics [5][6][7][8][9]. These reports focus on particular TFET gate configurations, single-gate (SG) [5][6][7], double-gate (DG) [4,8,9,11], or gate-all-around [10], or on specific aspects of the transport, such as the output characteristic at small drain biases [12,13].…”

Investigation of analog/RF performance of staggered heterojunctions based nanowire tunneling field-effect transistors

“…Therefore, theoretical study and experimental illustration of TFETs with higher drive current without sacrificing I OFF are under intense investigation for low-power applications [4,5], which can be broadly classified into two types. The first type uses the modification of the structures of TFET such as use of double-gate (DG) architecture [6], thin silicon body [7], low-k spacer [8], heteromaterial gate [9], and gate-to-source/drain overlap/ underlap [10,11]. Alternative type concentrates on the proper selection of material systems required to design a high-performance TFET in order to extend the ITRS roadmap [12] by employing heterostructure silicon/intrinsic-SiGe channel [13,4,14,15], or Ge in the source region [16], a high-k gate dielectric [17], source/drain doping engineering [18,19], and use of graphene as a channel material [20] to improve the switching current ratio between the ON-state and the OFF-state (I ON /I OFF ratio).…”

Compact channel potential analytical modeling of DG-TFET based on Evanescent-mode approach

“…[18] proposed analytically 2D non-linear Poisson's equation considering the inversion charge carrier for the reduction of tunneling barrier width with low gate and high gate voltage. In another paper [19,20], compact model has been derived for surface potential in DGTFET by splitting it into a gated tunnel diode and DGMOSFET based on charge model for circuit implication. The compact model is the mathematical model of active devices.…”