Vertically Stacked Silicon Nanowire Transistors Fabricated by Inductive Plasma Etching and Stress-Limited Oxidation

Polarity-Controllable Silicon Nanowire Transistors With Dual Threshold Voltages

“…The length and diameter of the defined nanowires are 350 and 50 nm, respectively. Then, four vertically stacked nanowires are formed in a top-down fashion, using a single deep reactive ion etching process step [12], [18] [see Fig. 1(b)].…”

Source and Drain Junction Engineering for Enhanced Non-Volatile Memory Performance

“…In this section, an all-around-gate (AAG) junctionless transistor is applied to oxide-nitrideoxide (O/N/O) type charge-trapping Flash memory. By utilizing a deep reactive ion etching (RIE) system (Ng et al, 2009), a junctionless transistor with a suspended SiNW channel with a width of 4 nm (W NW = 4 nm) and a length of 20 nm (L G = 20 nm) is fabricated, where the channel is completely separated from the bulk substrate. The performance is comparable to that of currently reported Flash memory, but it can be scaled down further, below the 20 nm node, due to the simplified process and the advantages inherited from the junctionless transistor.…”

“…The suspended SiNW via the Bosch process is achieved by balancing anisotropic etching and passivation steps. Details of the Bosch process can be found in the literature (Ng et al, 2009). The scanning electron microscopy (SEM) images in Fig.…”

Multigate Buckled Self-Aligned Dual Si Nanowire MOSFETs on Bulk Si for High Electron Mobility

“…Parallel to the CMOS boosters, making a 3-D stack of multigate devices using various techniques, e.g., dual SOI wafer [15], epitaxial Si-SiGe stacks [16], [17], and stress-limited oxidation [18] can enhance further the current density. Among the 3-D integration techniques, stress-limited oxidation is the simplest way used previously to make dual Si nanowires based on a vertical fin on silicon on insulator (SOI) [18], and vertical stack of Si nanowires from a preshaped vertical fin using scalloping on bulk Si [19]. A well-controlled stress-limited oxidation can even cause keeping a thin Si bridge between the vertical Si nanowire cores, leading to a significant improve in drive current [20], while keeping the nanowires in a more self-aligned manner and helping to suppress the sticking issue of the dense array of parallel nanowires due to the possible buckling in the case of, e.g., using local stressors and, therefore, providing more freedom to make a more dense array structure from the top-down Si nanowire platforms.…”