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This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm 2 , including calibration.

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An all-digital field programmable gate array based electromagnetic subtraction technique for direct UWB pulse generation is presented. Using this technique, it is possible to generate Gaussian pulses, monocycles or doublets with high flexibility using a single printed circuit board layout. User-controlled parameters include amplitude, pulsewidth, pulse-type, repetition rate or even modulation. Measurements indicate a Gaussian pulse with 1.24 V peak amplitude and a 10% pulse-width of 670 ps can be transmitted at a repetition frequency of 100 MHz. The corresponding − 10 dB bandwidth is 2.8 GHz.Introduction: Over the past decade, UWB radio has been commonly proposed for short-range high data rate communications [1] or for radar applications in the industrial [2] and medical fields. However, widespread implementation is still ongoing. This Letter contributes to providing an easy implementable development platform for UWB signal generation with higher flexibility compared with other transmitters. The key innovation of the Letter is the usage of a field programmable gate array (FPGA) together with an electromagnetic (EM) subtraction technique to form different Gaussian pulse shapes in a direct way. Two general transmitter implementations exist to date. CMOS integrated circuits can be considered for full-custom designs, while on the other hand, transmitters can be composed using commercial off-the-shelf components. The latter are implemented with step recovery diodes (SRDs) [2] or mesfets to generate steep edges and provide flexibility to some extent. An all-digital FPGA based implementation combines the high flexibility of CMOS designs together with rapid and easy implementation.

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In this paper, a two element antipodal Vivaldi antenna array in combination with an ultra-wideband (UWB) Wilkinson power divider feeding network is presented. The antennas are placed in a stacked configuration to provide more gain and to limit cross talk between transmit and receive antennas in radar applications. Each part can be realized with standard planar technology. For a single antenna element, a comparison in performance is done between standard FR4 and a Rogers ® RO3003 substrate. The antenna spacing is obtained using the parametric optimizer of CST MWS ® . The performance of the power divider and the antenna array is analyzed by means of simulations and measurements.