A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS

Ramkaj, Athanasios T.; Strackx, Maarten; Steyaert, Michiel; Tavernier, Filip

doi:10.1109/jssc.2018.2822823

Cited by 73 publications

(32 citation statements)

References 24 publications

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“…A modified bootstrap switch [58], [59] combining the adaptive body-biasing concept [60] is introduced in Fig. 13 (Q)-factor of switched-capacitor (sw-cap) banks.…”

Section: Charge-sharing Switch With Adaptive Body-biasingmentioning

confidence: 99%

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Chen

Siriburanon

et al. 2022

IEEE J. Solid-State Circuits

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This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant LC-tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate z-domain model, supporting any frequency division ratio N and CSL (or IL) strength β. The new theory sheds light not only on all IL-like PN phenomena (chiefly, its "loop" bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the "loop" cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75-26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.

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“…A modified bootstrap switch [58], [59] combining the adaptive body-biasing concept [60] is introduced in Fig. 13 (Q)-factor of switched-capacitor (sw-cap) banks.…”

Section: Charge-sharing Switch With Adaptive Body-biasingmentioning

confidence: 99%

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Chen

Siriburanon

et al. 2022

IEEE J. Solid-State Circuits

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“…To design all capacitors in Fig. 13, metal 7 is used because of its reduced parasitic contribution [31].…”

Section: B Ns-qtz Circuitsmentioning

confidence: 99%

A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

Liu

Xing

Gielen

2021

IEEE J. Solid-State Circuits

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This article presents a continuous-time (CT) analog-to-digital converter for wireless communication systems with a high tolerance against blockers. The zero-cancellation technique is introduced to eliminate the peaking in the signal transfer function (STF) to achieve better out-of-band-blocker immunity. An on-chip unary-approximating calibration is implemented to calibrate the mismatch of the outer current-steering digital-to-analog converter. A discrete-time (DT) second-order noise-shaping (NS) 2b/cycle asynchronous successive-approximation-register (ASAR) quantizer further reduces the quantization noise and the excess loop delay, achieving a CT-DT hybrid sixth-order NS without suffering from neither the problem of the CT-DT transfer function matching in a CT multistage NS topology nor the stability issue in a singleloop fully CT sixth-order topology. The prototype is fabricated in 28-nm bulk CMOS and is clocked at 1.7 GHz. With a bandwidth of 85 MHz, the analog-to-digital converter achieves 0-dB peaking STF, 74.4-dB signal to noise and SNDR and 87.5-dB spuriousfree dynamic range, while consuming 61.8-mW power, resulting in an excellent Schreier Figure-of-Merit (FoM S ) of 165.8 dB. Index Terms-2 b/cycle asynchronous successiveapproximation-register (ASAR), continuous-time (CT) analog-to-digital converter (ADC), flat signal transfer function (STF), noise-shaping (NS) QTZ, on-chip digital-to-analog converter (DAC) calibration, out-of-band blocker (OBB). I. INTRODUCTIONT HE ever more crowded radio spectrum causes great challenges to the design of wireless communication systems, in terms of increasing signal bandwidth (BW) as well as spectral performance. This makes continuous-time (CT) analog-to-digital converters (ADCs) more attractive for use in wireless applications due to their high dynamic range (DR), good power efficiency and implicit anti-aliasing property [1]-[3]. Fig. 1 shows the received spectrum at the antenna of the long-term-evolution advanced (LTE-A) standard [2], [4], [5]. For an inter-band contiguous carrier Manuscript

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“…The circuit design is implemented and well-tested. Our model can be applied in ADCs with the existence of low-power bootstrap/sample and hold (Ramkaj et al, 2018), low-power DAC and low power SAR Logic circuits with a frequency up to 5 MHz. In Figure 5, the most straightforward working of the proposed design with SAR ADC is shown.…”

Section: Working With Sar Adcmentioning

confidence: 99%

“…Switching nodes can also perform isolation in a regeneration mode to minimize the voltage variations (Figueiredo and Vital, 2006). The relationship between capacitors and the switching system is also significant for minimum parasitic resistance and capacitance (Ramkaj et al, 2018). For this, we reduce the distance between switches and capacitors.…”

Section: Introductionmentioning

confidence: 99%

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Faheem

Zhong

Wang

et al. 2020

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Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

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A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS

Cited by 73 publications

References 24 publications

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

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