A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS

Ramkaj, Athanasios T.; Strackx, Maarten; Steyaert, Michiel; Tavernier, Filip

doi:10.1109/esscirc.2017.8094552

Cited by 8 publications

(4 citation statements)

References 5 publications

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“…These cross-coupled inverters skew their thresholds because the cross-coupling forms a feed-forward structure. Most of the metastable comparator outputs are forced to "0" (the initial state of the comparator), but only half of them being correct [23]. Moreover, the voltage-domain comparator has more time to regenerate as only one comparison is performed inside each period.…”

Section: B Unipolar Tdcmentioning

confidence: 99%

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A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs

Lyu

Tavernier

2020

IEEE J. Solid-State Circuits

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A power and area efficient two-step hybrid voltagetime ADC achieves a 4 GS/s conversion speed and 39.9 dB SNDR in 28 nm CMOS. Two pipelined time-based converters (TBC) with a thermometer capacitive DAC (CDAC) in the ADC lead to a high-speed and low-power operation. The pipelined architecture splits the full ADC resolution and thus relaxing the TBC complexity. The TBC consists of a voltage-domain comparator, a current-source based voltage-to-time converter (VTC), and a ring oscillator (RO) based time-to-digital converter (TDC) with feed-forward and 2× interpolation that achieves high conversion speed and good linearity simultaneously. The prototype ADC is fabricated in a standard 28 nm CMOS process with an active area of only 0.017 mm 2 . The measured SNDR and SFDR are 39.9 dB and 47.8 dB with a Nyquist input at 4 GS/s. The FoM W and FoM S are 39.3 fJ/conv−step and 152.2 dB, respectively. Index Terms-Analog to digital converter (ADC), time-based ADC, time-to-digital converter (TDC), ring oscillator (RO), voltage-to-time converter (VTC), low power, high speed, single channel.

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Section: B Unipolar Tdcmentioning

confidence: 99%

“…The unit switch plus cap technique [23] is used in the CDAC to minimize the parasitic contribution to the CDAC settling. The unit capacitor is 6 fF.…”

Section: B Thermometer Capacitive Dacmentioning

confidence: 99%

A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs

Lyu

Tavernier

2020

IEEE J. Solid-State Circuits

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“…The schematic of the comparator circuit where the proposed calibration is employed is shown in Figure 4. The comparator core incorporates a first amplification stage followed by a second amplifier/half latch and the final latch, in a fully-dynamic structure for low power operation [24]. The multi-stage configuration allows for a more orthogonal optimization of each stage for various trade-offs, which allows the comparator to simultaneously achieve both high speed and low noise.…”

Section: Comparator Corementioning

confidence: 99%

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

et al. 2018

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This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of 0.82 mV and 0.99 mV, respectively clocked at 11 GHz, consuming only 0.89 mW from a 1 V supply, for an area of 0.00054 mm 2 , including calibration.

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“…Therefore, a TLFF comparator is introduced to optimize the delay for high speed application by adding an extra bypassing feed-forward path. [7][8] A comparator with a FIA realizes current reuse, boots gm/Id, insensitivity to the variation of VCM and decreases energy consumption. A floating capacitor is used to power FIA and make the preamplifier insensitive to VCM.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Low-Power CMOS Dynamic Comparators

Fan¹

2022

HSET

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This paper studies four structures of CMOS dynamic comparators introduced in recent years. Based on conventional double-tail comparator, a comparator with a tail capacitor prevents output nodes of preamplifier from completely discharging to reduce energy consumption. Another comparator with a cross-coupled pairs achieves the same purpose of the first design. A comparator adds a floating inverter amplifier (FIA) to realize both dynamic bias and current reuse, achieve low energy consumption and be insensitive to the VCM. The triple-latch feed-forward (TLFF) comparator decreases delay conspicuously.

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A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS

Cited by 8 publications

References 5 publications

A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs

A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

Performance Analysis of Low-Power CMOS Dynamic Comparators

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