3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoM&lt;inf&gt;S&lt;/inf&gt; in 28nm CMOS

Ramkaj, Athanasios T.; Ramos, Juan Manuel Sánchez; Lyu, Yifan; Strackx, Maarten; Pelgrom, J. M. Marcel; Steyaert, Michiel; Verhelst, Marian; Tavernier, Filip

doi:10.1109/isscc.2019.8662490

Cited by 12 publications

(8 citation statements)

References 6 publications

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“…As another example, for the 12-bit 5-GHz 159-mW ADC in [22] to incur 3 dB of SNR penalty due to clock jitter, we have P V C O ≈ 330 mW. The charge pump noise further raises these power numbers.…”

Section: B Lower Power Boundmentioning

confidence: 99%

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Jitter-Power Trade-Offs in PLLs

Razavi

2021

IEEE Trans. Circuits Syst. I

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As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself.

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Section: B Lower Power Boundmentioning

confidence: 99%

“…The quest for higher ADC speeds and resolutions continues [19]- [22]. The sampling clock jitter in ADC design presents daunting challenges.…”

Section: Pll Jitter-power Trade-offs For Adcsmentioning

confidence: 99%

Jitter-Power Trade-Offs in PLLs

Razavi

2021

IEEE Trans. Circuits Syst. I

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“…This section discusses a comprehensive comparison of the performance of CT pipelined ADCs, as outlined in Table 1. The comparison includes CT pipelined ADCs and notable ADCs using other architectures, such as single-loop CT [29], MASH CT [8], and DT interleaved and pipelined SAR ADCs [30]. It can be seen from Table 1 that most of the CT pipelined ADCs have an OSR of 4 or less.…”

Section: F Comparisons Of Ct Pipelined and Other Adcsmentioning

confidence: 99%

“…Furthermore, consider a comparison with the state-of-theart DT interleaved and pipelined ADC [30], which achieves similar application BW and NSD compared to the CT pipelined ADCs [17] and [20]. The DT ADC [30] achieves a wider BW with a 7 dB or 2 dB better FOM S than [17] and [21], respectively.…”

Section: F Comparisons Of Ct Pipelined and Other Adcsmentioning

confidence: 99%

Continuous-Time Pipelined ADC: A Breed of Continuous-Time ADCs for Wideband Data Conversion

Shibata

2023

IEEE Open J. Solid-State Circuits Soc.

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The continuous-time (CT) pipelined analog-to-digital converter (ADC) is an emerging ADC architecture suitable for wide-bandwidth (BW) digitization in fully integrated receiver applications. It inherits the integration-friendly features of CT ADCs, such as inherent anti-aliasing, while achieving the wide-BW operation originating from discrete-time (DT) pipelined ADCs. In this review article, we introduce a gain-centric ADC model and apply the key criteria derived from the model to transform a DT pipelined ADC into a CT pipelined ADC. We then discuss the design considerations and essential building blocks of the CT pipelined ADC. Finally, we examine several implementations of this architecture with their highlights and challenges.INDEX TERMS Analog-to-digital converter (ADC), continuous-time (CT) ADC, oversampling ADC, pipelined ADC, wideband ADC.

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“…Traditionally, stage scaling [1], opamp sharing [2,3], and open-loop residue amplifier [4,5] were classical lowpower design approaches. With the advent of a pipelined SAR ADC architecture [6], using a dynamic amplifier (DA) as a residue amplifier has been attracting considerable attentions [7][8][9][10][11][12][13][14][15][16][17][18][19][20]. Since the DA does not draw static current, this approach can lead to a fully dynamic and hence very power-efficient implementation given that the successiveapproximation register (SAR) ADC [21][22][23] in the stage typically does not consume static power.…”

Section: Introductionmentioning

confidence: 99%

A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers

2023

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This paper presents a 9-bit pipelined successive-approximation-register (SAR) ADC consisting of 4-stage sub-SAR ADCs using replica-biased dynamic residue amplifiers. The replica-biased amplifier in the 1st stage keeps the output common mode constant over various input voltage conditions, which enables cascading multiple dynamic-amplifier-based pipeline stages. The replica-biased amplifiers from the 2nd to the last stage maintain the differential gain, eliminating the need for bit-weight calibrations. The 1st~3rd stages utilize a loop-unrolled SAR structure for high-speed conversion. A 9-bit 500MS/s pipelined SAR ADC is fabricated in 28nm CMOS process, and it achieves SNDR of 49.1dB and SFDR of 60.4dB at low frequency and SNDR of 45.3dB and SFDR 56.0dB at Nyquist frequency. The measured performance over wide input common-mode and temperature range validates the operation of the replicabiased dynamic amplifiers. The measured Walden figure of merit (FoMw) is 23.3fJ/conversion-step and Schreier FoM (FoMs) is 158.6dB, respectively.INDEX TERMS Analog-to-digital converter (ADC), pipelined successive approximation resister (SAR), dynamic amplifier, replica-biasing.

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3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoM<inf>S</inf> in 28nm CMOS

Cited by 12 publications

References 6 publications

Jitter-Power Trade-Offs in PLLs

Jitter-Power Trade-Offs in PLLs

Continuous-Time Pipelined ADC: A Breed of Continuous-Time ADCs for Wideband Data Conversion

A 9-Bit 500-ms/s 4-Stage Pipelined SAR ADC With Wide Input Common-Mode Range Using Replica-Biased Dynamic Residue Amplifiers

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