This paper presents the design of circuits and architectures for optical communication transceivers. First, a system overview illustrating the challenges in high-speed implementations is given. Next, the design of transimpedance amplifiers and limiters is discussed and the problem of clock and data recovery is addressed. Finally, jitter issues and methods of estimating the jitter are introduced.14-1 -1 0-7803-6591-7/0Y$10.00 0 2001 IEEE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE

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This paper describes the issues and tradeoffs in the design and monolithic implementation of direct-conversion receivers and proposes circuit techniques that can alleviate the drawbacks of this architecture. Following a brief study of heterodyne and image-reject topologies, the direct-conversion architecture is introduced and effects such as dc offset, I=Q mismatch, even-order distortion, flicker noise, and oscillator leakage are analyzed. Related design techniques for amplification and mixing, quadrature phase calibration, and baseband processing are also described.

increased with reducing I osc , where I osc is not smaller than 1.3 mA. Therefore, the theoretical calculation in the ''/3'' mode is also verified by the measured results. CONCLUSIONSThe divide-by-2/3 ILFD was presented, which consumes 3.15 mW for the input frequency of 4.28-4.81 GHz with the input power of À0.5 dBm. The optimized value of the bias current for the maximum locking range of the ILFD was analyzed based on gain and phase conditions. Finally, the analysis was verified by the measured results. Table 1 summarized the performance of the FDs with two division modes. In comparisons with these FDs, the proposed circuit consumes much less power. Therefore, the proposed ILFD with variable division ratio is suitable to be used in a high-frequency and low-power frequency synthesizer. H. Jhin-Fang, LC-tank colpitts injection-locked frequency divider with even and odd modulo, IEEE Microwave Wireless Compon L. Chien-Feng, A low voltage 0.35 lm CMOS frequency divider with the body injection technique, IEEE Microwave Wireless Compon Lett 18 (2008), 470-472. 8. H.R. Rategh, H. Samavati, and T.H. Lee, A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-Ghz wireless LAN receiver, IEEE J Solid-State Circuits 35 (2000), 780-787.ABSTRACT: The radiation performance of a compact gap-coupled assembly of patches forming the geometry of elliptical patch antenna is simulated and tested using glass epoxy FR4 substrate material. This assembly is achieved by cutting a conventional elliptical patch antenna geometry into three independent patches through two narrow slits parallel to minor axis of elliptical patch. The two outer patches are identical in shape and size, and the central patch is excited through inset probe feed. Two outer patches are gap coupled to the center patch. This arrangement of antenna elements resonate at three frequencies 3.41, 3.62, and 5.54 GHz, respectively. The first two frequencies are closely spaced and gives an improved bandwidth (>10%). The radiation patterns of antenna at all three frequencies are almost identical in shape and nature. Details of the antenna design approach and experimental results are presented and discussed systematically. Measurements are in excellent agreement with simulation results which make the proposed structure promising for Wi-Max applications.

This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative noise, are identified and formulated. Based on the same concepts, a CMOS relaxation oscillator is also analyzed. Issues and techniques related to simulation of noise in the time domain are described, and two prototypes fabricated in a 0.5-pm CMOS technology are used to investigate the accuracy of the theoretical predictions. Compared with the measured results, the calculated phase noise values of a 2-GHz ring oscillator and a 900-MHz relaxation oscillator at 5 MHz offset have an error of approximately 4 dB.

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A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-m CMOS technology in an area of 1 1 0 9 mm 2 , the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1 28 10 6 , with random data input of length 2 23 1. The power dissipation is 72 mW from a 2.5-V supply.