A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector

Savoj, Jafar; Razavi, Behzad

doi:10.1109/4.918913

Cited by 237 publications

(172 citation statements)

References 10 publications

(15 reference statements)

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“…3, is a tapered current-mode logic (CML) buffer chain [18] (V dd = 1.8V ). The resistor in the last stage is set to match 50Ω transmission line.…”

Section: Resultsmentioning

confidence: 99%

Automated nonlinear Macromodelling of output buffers for high-speed digital applications

Dong¹,

Roychowdhury²

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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We present applications of a recently developed automated nonlinear macromodelling approach to the important problem of macromodelling high-speed output buffers/drivers. Good nonlinear macromodels of such drivers are essential for fast signal-integrity and timing analysis in high-speed digital design. Unlike traditional black-box modelling techniques, our approach extracts nonlinear macromodels of digital drivers automatically from SPICE-level descriptions. Thus it can naturally capture transistor-level nonlinearities in the macromodels, resulting in far more accurate signal integrity analysis, while retaining significant speedups. We demonstrate the technique by automatically extracting macromodels for two typical digital drivers. Using the macromodel, we obtain about 8× speedup in average with excellent accuracy in capturing different loading effects, crosstalk, simultaneous switching noise (SSN), etc..

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“…3, is a tapered current-mode logic (CML) buffer chain [18] (V dd = 1.8V ). The resistor in the last stage is set to match 50Ω transmission line.…”

Section: Resultsmentioning

confidence: 99%

Automated nonlinear Macromodelling of output buffers for high-speed digital applications

Dong¹,

Roychowdhury²

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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“…5 shows the circuit implementation of the charge-pump. The current associated with the error signal is twice as large as the current associated with the reference signal, due to the half-rate nature of the PD [8]. An on-chip DAC is used to adjust the CP current during capture range measurements.…”

Section: Cdr Architecture and Implementationmentioning

confidence: 99%

“…3 shows a block level implementation of the proposed half-rate FD embedded in the PD loop. We use a linear halfrate PD [8], along with a differential ring VCO. After a data rising edge, one of the two clock phases CK I and CK Q are chosen by the proposed FD, and is fed back to the PD.…”

Section: Introductionmentioning

confidence: 99%

An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection

Jalali

Shivnaraine

Sheikholeslami

et al. 2013

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference

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Abstract-A half-rate single-loop CDR with a new frequency detection scheme is introduced. The proposed frequency detector selects between the clock phases (I and Q) to reduce cycle slipping, hence improving lock time and capture range. This frequency detector, implemented within a 10Gb/s CDR in Fujitsu 65nm CMOS, consumes only 8mW, but improves the capture range by up to 3.6×. The measured capture range with the FD is from 8.675Gb/s to 11Gb/s.

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“…The second example is a current-mode logic (CML) buffer chain [18] (Vdd = 1.8V), the circuit diagram of which is shown in Fig. 4.…”

Section: B CML Buffermentioning

confidence: 99%

Model reduction via projection onto nonlinear manifolds, with applications to analog circuits and biochemical systems

Gu¹,

Roychowdhury²

2008

2008 IEEE/ACM International Conference on Computer-Aided Design

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Abstract-Previous model order reduction methods fit into the framework of identifying the low-order linear subspace and using the linear projection to project the full state space into the low-order subspace. Despite its simplicity, the macromodel might automatically include redundancies.In this paper, we present a model order reduction approach, named maniMOR, which extends the linear projection framework to a general nonlinear projection framework. The two key ideas of maniMOR are (1) it explicitly separates the construction of the low-order subspace and projection operation; (2) it constructs a nonlinear manifold which captures important system responses and defines the corresponding nonlinear projection operator.The low-order manifold subspace in maniMOR is identified by stitching together the low-order linear subspaces around a set of sample points on the manifold. After the manifold is determined, it is embedded into a global nonlinear coordinate system. The projection function is defined in a piece-wise linear manner, and the model evaluation is conducted directly in the manifold subspace using cheap matrix-vector product computations. As a result, a compact model is generated by precomputing all the functions and Jacobians and storing them in a look-up table.We apply maniMOR on two analog circuits and a bio-chemical system to validate its correctness. Extensive comparisons with the results of the full model and other macromodels are provided. Experimental results show that maniMOR manages to obtain a huge reduction -e.g., from 52 to 5 for the I/O buffer circuit and from 304 to 30 for yeast pheromone pathway system. This is less than half of the size of the TPWL model with the same accuracy. With great promise to capture important system responses, maniMOR presents a novel and powerful paradigm for nonlinear model reduction, and casts inspirations for further researches.

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A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector

Cited by 237 publications

References 10 publications

Automated nonlinear Macromodelling of output buffers for high-speed digital applications

Automated nonlinear Macromodelling of output buffers for high-speed digital applications

An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection

Model reduction via projection onto nonlinear manifolds, with applications to analog circuits and biochemical systems

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