Abstract:We present applications of a recently developed automated nonlinear macromodelling approach to the important problem of macromodelling high-speed output buffers/drivers. Good nonlinear macromodels of such drivers are essential for fast signal-integrity and timing analysis in high-speed digital design. Unlike traditional black-box modelling techniques, our approach extracts nonlinear macromodels of digital drivers automatically from SPICE-level descriptions. Thus it can naturally capture transistor-level nonlin… Show more
“…Model generators can also be categorized into the black, grey or white box approaches, depending on the level of existing knowledge of the system's structure and parameters. Dong et al (Dong and Roychowdhury 2005) indicates that white-box methods can produce more accurate macromodels than black-box methods. However, this work was only applied to a limited number of digital circuits.…”
Section: Fig 1 Linear Time-invariant Blockmentioning
confidence: 99%
“…PWP is further implemented in (Dong and Roychowdhury 2004) for extracting broadly applicable general-purpose macromodels from SPICE netlists such that the generated model is able to capture different loading effects, simultaneous switching noise (SSN), crosstalk noise and so on. Furthermore, a speed up of eight times simulation speed is achieved (Dong and Roychowdhury 2005). However, multiple training data has to be used to cover different operating regions.…”
Section: Impulse Response H(ttau) T-v Odes/pdes Transfer Function H(mentioning
“…Model generators can also be categorized into the black, grey or white box approaches, depending on the level of existing knowledge of the system's structure and parameters. Dong et al (Dong and Roychowdhury 2005) indicates that white-box methods can produce more accurate macromodels than black-box methods. However, this work was only applied to a limited number of digital circuits.…”
Section: Fig 1 Linear Time-invariant Blockmentioning
confidence: 99%
“…PWP is further implemented in (Dong and Roychowdhury 2004) for extracting broadly applicable general-purpose macromodels from SPICE netlists such that the generated model is able to capture different loading effects, simultaneous switching noise (SSN), crosstalk noise and so on. Furthermore, a speed up of eight times simulation speed is achieved (Dong and Roychowdhury 2005). However, multiple training data has to be used to cover different operating regions.…”
Section: Impulse Response H(ttau) T-v Odes/pdes Transfer Function H(mentioning
“…It can significantly reduce the simulation time and memory requirements [9], [10], [11]. In this section, implementation of reduced order compact macromodel of standard cells is discussed.…”
This paper presents a dynamic simulation methodology using a reduced order compact macromodel of standard cells. The standard cell macromodels are formulated with a smaller number of state variables compared to an equivalent transistor-level implementation. This results in significant speed-ups over transistor-level simulation for large scale circuits. Such reduction in state variables also reduces memory usage. The macromodels are based on transistor equations, and simulation using these models produces results in excellent agreement (delay errors below 1 %) with transistor-level simulation results. Various examples showing 1.5x-lOOx reduction in dynamic simulation time and 1.5x-2.8x reduction in memory usage are presented.
INTRODUCTIONWith continuous technology scaling and increasing demand for more functionality per chip, the number of transistors per chip is increasing. This is making transistor-level simulation of VL SI circuits challenging because of increased simulation runtimes and memory requirements. Given that the transistor-level simulation is capable of producing the most accurate results, in order to alleviate the computational and memory burden of a full-chip simulation of today ' s VLSI circuits, a simulation methodology is required which can produce sufficiently accurate results while significantly lowering computational and storage cost compared to transistor-level simulation.
“…System (1) is said to be externally stable if the system's output y(t) can be bounded by a function of the system's input u(t). Specifically, the system is said to be small signal input/output stable if there exist constants r 2 > 0 and γ 2 < ∞ such that ||y|| 2 ≤ γ 2 ||u|| 2 (6) for all t > t 0 given initial state x(0) = 0 and input u(t) such that ||u|| ∞ < r 2 . The external and internal stability of System (1) …”
Section: A System Stabilitymentioning
confidence: 99%
“…Recently there has been a large amount of interest in piecewise-linear (PWL) model order reduction (MOR) techniques [1], [2], [3], [4], [5], [6], [7], [8]. Currently, PWL methods, such as the Trajectory Piecewise-Linear (TPWL) method [9] are probably the only viable known way to handle strongly nonlinear systems.…”
Abstract-In this paper we present several results concerning the stabilization of piecewise-linear reduced order models. We include proofs of internal and external stability for models whose system matrices possess special structures. We then introduce a new projection scheme, and a new set of weighting functions which allow us to extend some of these results to piecewiselinear systems comprised of arbitrary matrices, at least one of which is Hurwitz. Included are an algorithm for creating switching piecewise-linear reduced models comprised of globally exponentially stable systems, and stable simulation results for a system which produces unstable results when using the standard TPWL method.
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