Abstract-A half-rate single-loop CDR with a new frequency detection scheme is introduced. The proposed frequency detector selects between the clock phases (I and Q) to reduce cycle slipping, hence improving lock time and capture range. This frequency detector, implemented within a 10Gb/s CDR in Fujitsu 65nm CMOS, consumes only 8mW, but improves the capture range by up to 3.6×. The measured capture range with the FD is from 8.675Gb/s to 11Gb/s.
This paper proposes a half-rate single-loop referenceless binary CDR that operates from 8.5 Gb/s to 12.1 Gb/s (36% capture range). The high capture range is made possible by adding a novel frequency detection mechanism which limits the magnitude of the phase error between the input data and the VCO clock. The proposed frequency detector produces three phases of the data, and feeds into the phase detector the data phase that minimizes the CDR phase error. This frequency detector, implemented within a 10 Gb/s CDR in Fujitsu's 65 nm CMOS, consumes 11 mW and improves the capture range by up to 6 when it is activated. He has been engaged in research and design of high-speed IO with CMOS.
This paper uses a 3-bit ADC to blindly sample the received data at 3x the baud rate to recover the data. By moving from 2x to 3x sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our fabricated test chip in Fujitsu's 65nm CMOS show a high frequency jitter tolerance of 0.19UIpp for a 5Gbps PRBS31 with a 16 FR4 channel.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.