Monolithic Phase-Locked Loops and Clock Recovery Circuits

Razavi, Behzad

doi:10.1109/9780470545331

Cited by 385 publications

(180 citation statements)

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“…The 13.56 MHz rectangular clock signal is then applied to a D flip-flop divide-by-8 circuit to make the 1.695 MHz clock signal. A simple PFD circuit with reduced AND gates and inverters [9] was used. The VCO was designed using a Schmitt trigger and a current-starved ring oscillator.…”

Section: The Dpll With a Charge Pump Enable Circuitmentioning

confidence: 99%

A 13.56 MHz Radio Frequency Identification Transponder Analog Front End Using a Dynamically Enabled Digital Phase Locked Loop

Choi¹,

Yang²,

Kim³

et al. 2010

Transactions on Electrical and Electronic Materials

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The analog front end (AFE) of a radio frequency identification transponder using the ISO 14443 type A standard with a 100% amplitude shift keying (ASK) modulation is proposed in this paper and verified by circuit simulations and measurements. This AFE circuit, using a 13.56 MHz carrier frequency, consists of a rectifier, a modulator, a demodulator, a regulator, a power on reset, and a dynamically enabled digital phase locked loop (DPLL). The DPLL, with a charge pump enable circuit, was used to recover the clock of a 100% modulated ASK signal during the pause period. A high voltage lateral double diffused metal-oxide semiconductor transistor was used to protect the rectifier and the clock recovery circuit from high voltages. The proposed AFE was fabricated using the 0.18 µm standard CMOS process, with an AFE core size of 350 µm × 230 µm. The measurement results show that the DPLL, using a demodulator output signal, generates a constant 1.695 MHz clock during the pause period of the 100% ASK signal.

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Section: The Dpll With a Charge Pump Enable Circuitmentioning

confidence: 99%

A 13.56 MHz Radio Frequency Identification Transponder Analog Front End Using a Dynamically Enabled Digital Phase Locked Loop

Choi¹,

Yang²,

Kim³

et al. 2010

Transactions on Electrical and Electronic Materials

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“…The transfer function in (14) and jitter PSD determine the PLL output jitter. For jitter at the input of the phase detector, the output jitter PSD is (15) To relate the jitter PSD to the output timing jitter, the Wiener-Khinchin theorem translates the jitter PSD to the time domain as described in [30]. (16) where represents the growth in the variance after an initial timing edge.…”

Section: B Jitter Statistics With Voltage Threshold Offsetmentioning

confidence: 99%

“…BER requirements in modern high-speed serial links compel limiting the accumulation of jitter [14]. Furthermore, a clock and data recovery (CDR) circuits, commonly implemented as phase-locked loops (PLLs), transfer jitter to the sampling clock [15]. The feedback mechanism of the CDR converts any DJ into RJ on the sampling clock and this sampling disturbance causes an additional BER penalty.…”

Section: Introductionmentioning

confidence: 99%

Analysis and Equalization of Data-Dependent Jitter

Buckwalter

Hajimiri

2006

IEEE J. Solid-State Circuits

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Abstract-Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase-and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10 12 BER from 30 to 52 ps at 10 Gb/s.

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“…2. The level-shifted diode-connected MOS load was first introduced as an alternative to simple a diode-connected load to improve the voltage headroom [3]. In addition to the improved voltage headroom the load also introduces a zero to the transfer function [4].…”

Section: Differential Amplifier With Active Peakingmentioning

confidence: 99%

A 10.0Gb/s all-active LVDS receiver in 0.18.MU.m CMOS technology

Wijetunga

2006

IEICE Electron. Express

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Results for a 10.0 Gb/s all-active LVDS receiver, designed using active bandwidth improvement strategies, are presented. The generalized model generated for the active peak load shows that the transfer characteristic of the load is similar to that of inductive shunt peaking, and can achieve bandwidth improvements comparable to that of on-chip inductive shunt peaking without the associated area penalty. The measured 3 dB bandwidth of the transceiver is 6.0 GHz, and the input sensitivity (BER < 10 −13 ) at 10.0 Gb/s and 11.0 Gb/s are 80 mVpp and 100 mVpp respectively. The total transceiver power consumption, including the 50 Ω source terminated output driver, is 60 mW.

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Monolithic Phase-Locked Loops and Clock Recovery Circuits

Cited by 385 publications

References 0 publications

A 13.56 MHz Radio Frequency Identification Transponder Analog Front End Using a Dynamically Enabled Digital Phase Locked Loop

A 13.56 MHz Radio Frequency Identification Transponder Analog Front End Using a Dynamically Enabled Digital Phase Locked Loop

Analysis and Equalization of Data-Dependent Jitter

A 10.0Gb/s all-active LVDS receiver in 0.18.MU.m CMOS technology

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