Jitter-Power Trade-Offs in PLLs

Razavi, Behzad

doi:10.1109/tcsi.2021.3057580

Cited by 49 publications

(18 citation statements)

References 26 publications

(35 reference statements)

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“…In the past decades, clock is mostly used in the fixedfrequency style with high-frequency-stability as its highest priority. In clock-circuit design, people have focused almost their full attention on minimizing clock jitter and lowering phase noise [1][2][3][4][5][6][7][8][9]. When used in applications, such clock signal however has only few useable frequency choices.…”

Section: Introductionmentioning

confidence: 99%

A New Perspective of Flexible Clocking Ideology for Driving and Devising Circuits in Emerging Resource-Constrained Applications

Wei

Xiu

2022

IEEE Access

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Clock is the most important signal in electronic system. In current practice, the dominant clocking style is the fixed-frequency approach. For a given application, the clock signal is only required to work at a few selected frequencies. Moreover, in the process of performing a task, it must not change its frequency. This style has worked well in the past. However, it is preventing information processing efficiency from being raised to next level. Worse yet, the emergence of resource-constrained applications, such as edge computing and IoT, can render this approach unserviceable. In this paper, a new perspective of flexible clocking ideology is advocated. It promotes the use of a clock generator, TAF-DPS, that possesses features of "arbitrary frequency generation" and "instantaneous frequency switching". Owing to its superior capability in synthesizing waveform, TAF-DPS can handle many signal processing problems in a more elegant manner and serve some special purposes more efficiently. Further, it can be used for generating data for security purposes. TAF-DPS is especially applicable for environments with large frequency instability, which is a major problem in resource-constrained applications. The contribution of this paper is the advocacy of a new perspective of flexible clocking. This ideology is gradually developed in this paper as the argument is carried out through examples of novel architectures enabled by TAF-DPS. The perspective naturally emerges from the collective effect of those novel architectures. The large number of emerging applications, exemplified by edge computing and IoT, inspire system-level innovations that inevitably present new challenges to circuitlevel. Those challenges are so demanding that they require overhaul in our circuit design philosophy. This new perspective is such an overhaul in fundamental level. Its aim is to answer the challenges, for better serving the emerging demands in higher levels.

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Section: Introductionmentioning

confidence: 99%

A New Perspective of Flexible Clocking Ideology for Driving and Devising Circuits in Emerging Resource-Constrained Applications

Wei

Xiu

2022

IEEE Access

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“…Direct-RF sampling data converters [1,2,3,4,5] simplifies transceiver systems by eliminating frequency conversion stages. For multi-GHz signal sampling, phase noise (PN) of the clock signal generated from the frequency synthesizer has a significant effect on the noise performance of data converters [6,7]. Frequency synthesizers based on charge pump phase-locked loops (CPPLL) with octave-range VCOs are widely adopted to satisfy the noise requirement and to cover various frequency bands [8,9,10,11,12].…”

Section: Introductionmentioning

confidence: 99%

A 92 fs<sub>rms</sub> jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control

Li¹,

Wang²,

Wang³

et al. 2021

IEICE Electron. Express

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This letter presents a frequency synthesizer based on a multicore Class-C voltage-controlled oscillator (VCO) with a digital automatic amplitude control (AAC) loop. A novel digital tail current estimation is adopted to mitigate the risks of unexpected VCO oscillation failure, due to current shortage during frequency calibration. Meanwhile, a digital amplitude recalibration is proposed to provide continuous amplitude control, avoiding noise distortion resulted from amplitude drift after a conventional disposable amplitude calibration. The digital AAC loop achieves a specific VCO amplitude with good stability and introduces no extra noise. Fabricated in a 28 nm CMOS process, the presented frequency synthesizer occupies an active area of 1.43 mm 2 . By measuring a 3 GHz carrier, the open loop VCO phase noise is -132 dBc/Hz at 1 MHz offset and the close loop root mean square jitter is 81 fs.

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“…EVM PLL and EVM TX are the respective EVM contributions from the PLL and transmitter. noise (PN) and rms jitter requirements on phase-locked loops (PLLs) [1], [2]. To support 256 QAM in the 28-/39-GHz millimeter-wave (mmW) bands [1] and 1024 QAM in the sub-6-GHz bands, error-vector magnitude (EVM) contributed by the PLL's PN should be as low as 1.4% and 0.4%, respectively.…”

mentioning

confidence: 99%

“…To support 256 QAM in the 28-/39-GHz millimeter-wave (mmW) bands [1] and 1024 QAM in the sub-6-GHz bands, error-vector magnitude (EVM) contributed by the PLL's PN should be as low as 1.4% and 0.4%, respectively. This accounts for around 16% of the total EVM's budget (i.e., EVM 2 PLL /EVM 2 in Fig. 1), while the other main contributors come from the transmitter's non-idealities (i.e., nonlinearity, LO leakage, I/Q imbalance, and so on).…”

mentioning

confidence: 99%

“…2(b)]. Assuming a perfect lock, if the oscillator's free-running frequency f osc suddenly gets a little lower than N× the reference frequency (i.e., N f ref ), then, at the following reference event, the sharing charge 2 It can be calculated analytically by the slope of "phase domain response (PDR)" [27], including the methods of "impulse sensitivity function (ISF)" [25], [26], "perturbation projection vector (PPV)" [32], [33] (i.e., a more rigorous version of ISF, considering the phase shift of ISF itself when perturbation happens [34], which enables the ISF to predict some IL phenomena [35]), and others [16], [27]. 3 For a fractional-N operation, the DAC would set an aliased [4] version of the sinusoidal waveform of V osc .…”

mentioning

confidence: 99%

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A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

Chen

Siriburanon

et al. 2022

IEEE J. Solid-State Circuits

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This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant LC-tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate z-domain model, supporting any frequency division ratio N and CSL (or IL) strength β. The new theory sheds light not only on all IL-like PN phenomena (chiefly, its "loop" bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the "loop" cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75-26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.

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Jitter-Power Trade-Offs in PLLs

Cited by 49 publications

References 26 publications

A New Perspective of Flexible Clocking Ideology for Driving and Devising Circuits in Emerging Resource-Constrained Applications

A New Perspective of Flexible Clocking Ideology for Driving and Devising Circuits in Emerging Resource-Constrained Applications

A 92 fs<sub>rms</sub> jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control

A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking

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