Thorough investigations of the saturation phenomena in state-of-the-art HV Lateral DMOS architectures (L-DMOS and X-DMOS), based on 2D numerical simulation and on the new concept of intrinsic drain potential, VK, are presented The paper highlights the VK evolution in all operation regimes, analyses the corresponding complex quasi-saturation mechanisms and originally demonstrates that this key potential remains at a low-voltage and shows a marked maximum value at low Vc. A simple and accurate analytical modelling strategy, which is usable for any architecture specific bias-dependence of the drift region equivalent resistance is proposed based on the VK-concept. Very good model performances using a BSIM3v3 low-voltage model combined with the proposed intrinsic MOSFET strategy are reported

This paper describes a 90 V, 300 m mm 2 RESURF P-type drain extended MOS (PDEMOS) transistor in a 0.35 m based smart power technology.The excellent performance of the device is realised with a dedicated Pdrift layer, designed to achieve maximum benefit from the RESURF effect. The proposed approach is very cost effective since there is only one extra mask for the Pdrift layer, no high-tilt implant (no extra mask for a Nbody) and no extra thermal budget.

A 0.82" QXGA (2048x1536) LCOS panel for professional projection applications is presented. To meet the high requirements, a new scalable and testable analog layout architecture is presented featuring small pixel sizes and maximum signal integrity, allowing large resolutions and high illumination levels. The QXGA-panel is designed in C35_2P4M and has 70 dies/ wafer. SID 07 DIGEST • 105 ISSN/007-0966X/07/3801-0105-$1.00 © 2007 SID

This paper deals with the investigation of the LDMOSFET saturation mechanisms via 2D numerical simulations and experiments. A clear separation between the saturation of intrinsic MOS transistor and complex quasi-saturation mechanisms is made using the intrinsic drain concept. A modelling strategy for drain current based on the experimental extraction of the drift series resistance is presented. Very good model performances using a BSIM3v3 lowvoltage model combined with the proposed drift resistance extracted values are reported.

This paper focuses on the design of an integrated high‐voltage HV driver chip for bi‐stable LCDs. First of all, the design of HV generators, based on the Dickson charge pump is discussed. A short summary of the most important simulation results is given. Subsequently, the paper describes the design of integrated HV multiplexers for switching the HV outputs of the generators to the pixel electrodes. Finally, the implementation of the design in a prototype chip, together with measurement results are mentioned and the paper is concluded with some thoughts on future improvements and possible applications.