Physical modelling strategy for (quasi-) saturation effects in lateral DMOS transistor based on the concept of intrinsic drain voltage

Abstract

This paper deals with the investigation of the LDMOSFET saturation mechanisms via 2D numerical simulations and experiments. A clear separation between the saturation of intrinsic MOS transistor and complex quasi-saturation mechanisms is made using the intrinsic drain concept. A modelling strategy for drain current based on the experimental extraction of the drift series resistance is presented. Very good model performances using a BSIM3v3 lowvoltage model combined with the proposed drift resistance extracted values are reported.

A numerical study of field plate configurations in RF SOI LDMOS transistors

“…(2) accounts for the drift mobility reduction and consequently the g m variation due to the JFET effect at the drift region. The V ch value, also defined as the potential at the boundary between body and drift regions, depends on the applied V GS and V DS values and is usually extracted from experimental measurements [12].…”

An Explicit Compact Model for High-Voltage LDMOS

“…One approach is to construct a sub-circuit so that its terminal behaviors match the ones of a LDMOS [1]. Another approach is to introduce an internal node between the channel and drift region (K-point) [2][3][4][5]. In both cases, iterations are usually required and efforts have to be made to ensure convergence and improve efficiency.…”