Cost Effective Implementation of a 90 V RESURF P-type Drain Extended MOS in a 0.35 um Based Smart Power Technology

Abstract

This paper describes a 90 V, 300 m mm 2 RESURF P-type drain extended MOS (PDEMOS) transistor in a 0.35 m based smart power technology.The excellent performance of the device is realised with a dedicated Pdrift layer, designed to achieve maximum benefit from the RESURF effect. The proposed approach is very cost effective since there is only one extra mask for the Pdrift layer, no high-tilt implant (no extra mask for a Nbody) and no extra thermal budget.

Anomalous Field Transistor BTI Failure Mechanism in an 80V Technology

“…The degradation of the vt with time is shown in Figure 3 (absolute vt shift), for different stress temperatures. The empirical model of this degradation follows a saturating power law [1], where t is time, A is the saturating value, B is the time when half of the saturating value is reached or the delay, and n is the power law exponent indicating the speed of the degradation. Both B and n are temperature dependent [2] [3].…”

“…The I3T80U technology includes both lateral and vertical 80V extended drain MOS devices (DMOS) that are integrated into a standard 0.35µm CMOS technology (1). During the transfer of this technology to a second fabrication site, the parasitic metal field transistor BTI failures were significant on all lots and all sites in the second fab, but not in the mother fab.…”

Enhancement of Electrical Safe Operation Area of 60 V nLDMOS by Engineering of Reduced Surface Electrical Field in the Drift Region

“…However, the resulting LDMOS devices have a higher threshold voltage, which deteriorates the device switching efficiency and enhances manufacturing difficulty due to the high-energy ion implantation. Therefore, some researchers have proposed optimizing the drift region structure or doping concentration to suppress the Kirk effect, thus manufacturing LDMOS with a high BV on [13][14][15][16][17].…”