In this letter, a top-gated field effect device (FED) manufactured from monolayer graphene is investigated.Except for graphene deposition, a conventional top-down CMOS-compatible process flow is applied.Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from top-gated Graphene-FEDs. The extracted values exceed the universal mobility of silicon and silicon-on-insulator MOSFETs.
The absence of a band gap in graphene restricts its straight forward application as a channel material in field effect transistors. In this letter, we report on a new approach to engineer a band gap in graphene field effect devices (FED) by controlled structural modification of the graphene channel itself. The conductance in the FEDs is switched between a conductive "onstate" to an insulating "off-state" with more than six orders of magnitude difference in conductance. Above a critical value of an electric field applied to the FED gate under certain environmental conditions, a chemical modification takes place to form insulating graphene derivatives. The effect can be reversed by electrical fields of opposite polarity or short current pulses to recover the initial state. These reversible switches could potentially be applied to non-volatile memories and novel neuromorphic processing concepts.
We report on a method for the fabrication of graphene on a silicon dioxide substrate by solid-state dissolution of an overlying stack of a silicon carbide and a nickel thin film. The carbon dissolves in the nickel by rapid thermal annealing. Upon cooling, the carbon segregates to the nickel surface forming a graphene layer over the entire nickel surface. By wet etching of the nickel layer, the graphene layer was allowed to settle on the original substrate. Scanning tunneling microscopy (STM) as well as Raman spectroscopy has been performed for characterization of the layers. Further insight into the morphology of the layers has been gained by Raman mapping indicating micrometer-size graphene grains. Devices for electrical measurement have been manufactured exhibiting a modulation of the transfer current by backgate electric fields. The presented approach allows for mass fabrication of polycrystalline graphene without transfer steps while using only CMOS compatible process steps.
In this work, double-gated field effect transistors manufactured from monolayer graphene are investigated. Conventional top-down CMOS-compatible processes are applied except for graphene deposition by manual exfoliation. Carrier mobilities in single-and doublegated graphene field effect transistors are compared. Even in double-gated graphene FETs, the carrier mobility exceeds the universal mobility of silicon over nearly the entire measured range. At comparable dimensions, reported mobilities for ultra thin body siliconon-insulator MOSFETs can not compete with graphene FET values.
With metal stripes being intrinsic components of plasmonic waveguides, plasmonics provides a “naturally” energy-efficient platform for merging broadband optical links with intelligent electronic processing, instigating a great promise for low-power and small-footprint active functional circuitry. The first active Dielectric-Loaded Surface Plasmon Polariton (DLSPP) thermo-optic (TO) switches with successful performance in single-channel 10 Gb/s data traffic environments have led the inroad towards bringing low-power active plasmonics in practical traffic applications. In this article, we introduce active plasmonics into Wavelength Division Multiplexed (WDM) switching applications, using the smallest TO DLSPP-based Mach-Zehnder interferometric switch reported so far and showing its successful performance in 4×10 Gb/s low-power and fast switching operation. The demonstration of the WDM-enabling characteristics of active plasmonic circuits with an ultra-low power × response time product represents a crucial milestone in the development of active plasmonics towards real telecom and datacom applications, where low-energy and fast TO operation with small-size circuitry is targeted.
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