The degradation of thin gate oxides connected with the interconnect under the interlayer dielectric(IlD) by Ar plasma inadiation was observed. The electric field of gate oxide breakdown and the total charge to breakdovn(QBD were dependent on the material of the ILD. The current density through the ILD, calculated from QBD, was nearly equal to the measured value. Plasma damage through the ILD is caused mainly by the leakage current of the ILD.
Recently, with the miniaturization of ULSI patterns, the percentage of the LSI production cost occupied by the multilevel interconnection process is increasing due to the increase in the process steps and the introduction of new materials. In order to realize miniaturization process and achieve cost reduction at the same time, viahole maskless multilevel interconnect technology (maskless pillar process) has been developed. By merging the via-hole mask information on the underlying interconnection mask and by a selective etching of the multilevel metal films which depends on the mask width, underlying interconnection and metal pillars are formed simultaneously. The reduction of process steps has become possible by eliminating the via-hole lithography, etching, and filling process. As a result of electrical measurement of samples formed by the maskless pillar process, the feasibility for two-level metal interconnection has been verified, which confirmed it to be a multilevel interconnection process suitable for sub-half micron devices with guaranteed reliability.
Dependence of electromigration (EM) lifetime for via chains with conventional sputtered AI-Si-Cu films on slope angles of via holes has been investigated. EM testing for tapered (slope angle of 55 ~ and vertical (slope angle of 85 ~ via chains with 11 ~m long first metal lines and 12 ~m long second metal lines was performed under the same stress condition. Mean time to failure (MTF) of the EIK for the tapered via chains is one order of magnitude shorter than that for the vertical via chains, although the step coverage of the Ai-Si=Cu films in the vias is improved by controlling the slope angle of the via hole for the tapered via. It was found that the MTF for the via chains degrades with decreasing the slope angle of the via hole. In this case, thicknesses of the local passivation layer in the via hole increase with decreasing the slope angle of the via hole because of improvement in the step coverage of the passivation layer. The MTF for the tapered via chains with a SiN/PSG dual passivation layer was i0 h, while that with a PSG single passivation layer was at least over 2000 h. It is inferred from these results that the thermal tensile stress induced in the A1 film due to the thicker passivation layer increases the diffusivity of Al atoms in the vicinity of the via interface, which results in degradation of the EM resistance for the tapered via chains.
This paper presents a dopant drive-out process from elevated source/drain (S/D) structures with titanium silicide local interconnects, which reduces not only the S/D areas but also junction capacitance in advanced complementary-metal-oxide-semiconductor (CMOS) fabrication. A low-oxygen-content process with an optimized boron (B) doping realizes a thermally stable titanium silicide with reduced Ti–B compound formation. Electrical measurements of the metal-oxide-semiconductor field effect transistors (MOSFETs) show good I-V characteristics and high endurance to short-channel effects. Furthermore, the MOSFETs have hot-carrier and bias-temperature aging properties similar to those of controlled devices. Consequently, it has been clarified that the delay time per stage of the MOSFETs with the local interconnects can be reduced with decreasing junction capacitance.
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