Multilevel interconnection technology without via‐hole mask (maskless pillar process)

Abstract

Recently, with the miniaturization of ULSI patterns, the percentage of the LSI production cost occupied by the multilevel interconnection process is increasing due to the increase in the process steps and the introduction of new materials. In order to realize miniaturization process and achieve cost reduction at the same time, viahole maskless multilevel interconnect technology (maskless pillar process) has been developed. By merging the via-hole mask information on the underlying interconnection mask and by a selective etching of the multilevel metal films which depends on the mask width, underlying interconnection and metal pillars are formed simultaneously. The reduction of process steps has become possible by eliminating the via-hole lithography, etching, and filling process. As a result of electrical measurement of samples formed by the maskless pillar process, the feasibility for two-level metal interconnection has been verified, which confirmed it to be a multilevel interconnection process suitable for sub-half micron devices with guaranteed reliability.