A Low Parasitic Capacitance Scheme by Thermally Stable Titanium Silicide Technology for High Speed Complementary-Metal-Oxide-Semiconductor

Abstract

This paper presents a dopant drive-out process from elevated source/drain (S/D) structures with titanium silicide local interconnects, which reduces not only the S/D areas but also junction capacitance in advanced complementary-metal-oxide-semiconductor (CMOS) fabrication. A low-oxygen-content process with an optimized boron (B) doping realizes a thermally stable titanium silicide with reduced Ti–B compound formation. Electrical measurements of the metal-oxide-semiconductor field effect transistors (MOSFETs) show good I-V characteristics and high endurance to short-channel effects. Furthermore, the MOSFETs have hot-carrier and bias-temperature aging properties similar to those of controlled devices. Consequently, it has been clarified that the delay time per stage of the MOSFETs with the local interconnects can be reduced with decreasing junction capacitance.