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Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to large inaccuracies in the results, especially when traces contain only a subset of executed instructions for trace reduction. The main problem in the filtered trace simulation is that the trace does not contain enough information with which one can predict the actual penalty of a cache miss. In this paper, we discuss and evaluate three strategies to quantify the impact of a long latency memory access in a superscalar processor when traces have only L1 cache misses. The strategies are based on models about how a cache miss is treated with respect to other cache misses: (1) isolated cache miss model, (2) independent cache miss model, and(3) pairwise dependent cache miss model. Our experimental results demonstrate that the pairwise dependent cache miss model produces reasonably accurate results (4.8% RMS error) under perfect branch prediction. Our work forms a basis for fast, accurate, and configurable multicore processor simulation using a pre-determined processor core design.

A key design issue for chip multiprocessors (CMPs) is how to exploit the finite chip area to get the best system throughput. The most dominant area-consuming components in a CMP are processor cores and caches today. There is an important trade-off between the number of cores and the amount of cache in a single CMP chip. If we have too few cores, the system throughput will be limited by the number of threads. If we have too small cache capacity, the system may perform poorly due to frequent cache misses. This paper presents a simple and effective analytical model to study the trade-off of the core count and the cache capacity in a CMP under a finite die area constraint. Our model differentiates shared, private, and hybrid cache organizations. Our work will complement more detailed yet time-consuming simulation approaches by enabling one to quickly study how key chip area allocation parameters affect the system performance.

We consider the focusing energy-critical inhomogeneous nonlinear Schrödinger equation:3 , and p = 5 − 2b. On the road map of Kenig-Merle [22] we show the global well-posedness and scattering of radial solutions under energy condition, and rigidity condition −bg(x) ≤ x · ∇g(x). We also provide sharp finite time blowup results for non-radial and radial solutions. For this we utilize the localized virial identity.2010 Mathematics Subject Classification. M35Q55, 35Q40.

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<p style='text-indent:20px;'>In this paper, we consider the Cauchy problem of <inline-formula><tex-math id="M1">\begin{document}$ d $\end{document}</tex-math></inline-formula>-dimension Hartree type Dirac equation with nonlinearity <inline-formula><tex-math id="M2">\begin{document}$ c|x|^{-\gamma} * \langle \psi, \beta \psi\rangle $\end{document}</tex-math></inline-formula>, where <inline-formula><tex-math id="M3">\begin{document}$ c\in \mathbb R\setminus\{0\} $\end{document}</tex-math></inline-formula>, <inline-formula><tex-math id="M4">\begin{document}$ 0 &lt; \gamma &lt; d $\end{document}</tex-math></inline-formula>(<inline-formula><tex-math id="M5">\begin{document}$ d = 2,3 $\end{document}</tex-math></inline-formula>). Our aim is to show the local well-posedness in <inline-formula><tex-math id="M6">\begin{document}$ H^s $\end{document}</tex-math></inline-formula> for <inline-formula><tex-math id="M7">\begin{document}$ s &gt; \frac{\gamma-1}2 $\end{document}</tex-math></inline-formula> with mass-supercritical cases(<inline-formula><tex-math id="M8">\begin{document}$ 1 &lt; \gamma&lt;d $\end{document}</tex-math></inline-formula>) and mass-critical case(<inline-formula><tex-math id="M9">\begin{document}$ {\gamma} = 1 $\end{document}</tex-math></inline-formula>) via bilinear estimates and angular decomposition for which we use the null structure of nonlinear term effectively. We also provide the flow of Dirac equations cannot be <inline-formula><tex-math id="M10">\begin{document}$ C^3 $\end{document}</tex-math></inline-formula> at the origin for <inline-formula><tex-math id="M11">\begin{document}$ H^s $\end{document}</tex-math></inline-formula> with <inline-formula><tex-math id="M12">\begin{document}$ s &lt; \frac{\gamma-1}2 $\end{document}</tex-math></inline-formula>.</p>

Simulation is indispensable in computer architecture research. Researchers increasingly resort to detailed architecture simulators to identify performance bottlenecks, analyze interactions among different hardware and software components, and measure the impact of new design ideas on the system performance. However, the slow speed of conventional execution‐driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper describes a novel fast multicore processor architecture simulation framework called Two‐Phase Trace‐driven Simulation (TPTS), which splits detailed timing simulation into a trace generation phase and a trace simulation phase. Much of the simulation overhead caused by uninteresting architectural events is only incurred once during the cycle‐accurate simulation‐based trace generation phase and can be omitted in the repeated trace‐driven simulations. We report our experiences with tsim, an event‐driven multicore processor architecture simulator that models detailed memory hierarchy, interconnect, and coherence protocol based on the TPTS framework. By applying aggressive event filtering, tsim achieves an impressive simulation speed of 146 millions of simulated instructions per second, when running 16‐thread parallel applications. Copyright © 2010 John Wiley & Sons, Ltd.

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