TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation

Cho, Sangyeun; Demetriades, Socrates; Evans, Shayne; Jin, Lei; Lee, Hyunjin; Lee, Kiyeon; Moeng, Michael

doi:10.1109/icpp.2008.7

Cited by 21 publications

(22 citation statements)

References 17 publications

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“…Separating functional models from timing models is a well-established technique used in many simulators including: FastSim [31], TimingFirst [25], GEMS [24], tsim [12], Asim [16], HASim [15], FAST [11], and ProtoFlex [13].…”

Section: Related Workmentioning

confidence: 99%

Graphite: A distributed parallel simulator for multicores

Miller

Kasture

Kurian

et al. 2010

HPCA - 16 2010 the Sixteenth International Symposium on High-Performance Computer Architecture

342

227

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This paper introduces the open-source Graphite distributed parallel multicore simulator infrastructure. Graphite is designed from the ground up for exploration of future multicore processors containing dozens, hundreds, or even thousands of cores. It provides high performance for fast design space exploration and software development for future processors. Several techniques are used to achieve this performance including: direct execution, multi-machine distribution, analytical modeling, and lax synchronization. Graphite is capable of accelerating simulations by leveraging several machines. It can distribute simulation of an off-the-shelf threaded application across a cluster of commodity Linux machines with no modification to the source code. It does this by providing a single, shared address space and consistent single-process image across machines. Graphite is designed to be a simulation framework, allowing different component models to be easily replaced to either model different architectures or tradeoff accuracy for performance.We evaluate Graphite from a number of perspectives and demonstrate that it can simulate target architectures containing over 1000 cores on ten 8-core servers. Performance scales well as more machines are added with near linear speedup in many cases. Simulation slowdown is as low as 41× versus native execution for some applications.The Graphite infrastructure and existing models will be released as open-source software to allow the community to simulate their own architectures and extend and improve the framework.

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Section: Related Workmentioning

confidence: 99%

Graphite: A distributed parallel simulator for multicores

Miller

Kasture

Kurian

et al. 2010

HPCA - 16 2010 the Sixteenth International Symposium on High-Performance Computer Architecture

342

227

View full text Add to dashboard Cite

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“…We evaluate the proposed StimulusCache policies with a detailed trace-driven CMP architecture simulator [6]. The parameters of the processor we model are given in Table 2.…”

Section: Methodsmentioning

confidence: 99%

StimulusCache: Boosting performance of chip multiprocessors with excess cache

Lee

Cho

Childers

2010

HPCA - 16 2010 the Sixteenth International Symposium on High-Performance Computer Architecture

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“…Lee et al proposed and studied several behavioral core models [18], [1]. These models consist of a trace of L2 accesses annotated with some information, in particular timestamps, like in the ASPEN model.…”

Section: B Behavioral Core Modelsmentioning

confidence: 99%

“…Trace-driven simulation cannot simulate accurately the behavior of non-deterministic parallel programs for which the sequence of instructions executed by a thread may be strongly dependent on the timing of requests to the uncore [20]. Some previous studies have shown that tracedriven simulation could reproduce somewhat accurately the behavior of certain parallel programs [20], [12], and it may be possible to implement behavioral core models for such programs [18], [21]. Nevertheless, behavioral core modeling may not be the most appropriate simulation tool for studying the execution of parallel programs.…”

Section: Behavioral Core Models For Multi-core Simulationmentioning

confidence: 99%

BADCO: Behavioral Application-Dependent Superscalar Core model

Velásquez¹,

Michaud²,

Seznec³

2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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Abstract-Microarchitecture research and development rely heavily on simulators. The ideal simulator should be simple and easy to develop, it should be precise, accurate and very fast. But the ideal simulator does not exist, and microarchitects use different sorts of simulators at different stages of the development of a processor, depending on which is most important, accuracy or simulation speed. Approximate microarchitecture models, which trade accuracy for simulation speed, are very useful for research and design space exploration, provided the loss of accuracy remains acceptable. Behavioral superscalar core modeling is a possible way to trade accuracy for simulation speed in situations where the focus of the study is not the core itself. In this approach, a superscalar core is viewed as a black box emitting requests to the uncore at certain times. A behavioral core model can be connected to a cycle-accurate uncore model. Behavioral core models are built from cycle-accurate simulations. Once the time to build the model is amortized, important simulation speedups can be obtained. We describe and study a new method for defining behavioral models for modern superscalar cores. The proposed Behavioral Application-Dependent Superscalar Core model, BADCO, predicts the execution time of a thread running on a superscalar core with an error less than 10 % in most cases. We show that BADCO is qualitatively accurate, being able to predict how performance changes when we change the uncore. The simulation speedups we obtained are typically between one and two orders of magnitude.

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TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation

Cited by 21 publications

References 17 publications

Graphite: A distributed parallel simulator for multicores

Graphite: A distributed parallel simulator for multicores

StimulusCache: Boosting performance of chip multiprocessors with excess cache

BADCO: Behavioral Application-Dependent Superscalar Core model

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