Accurately approximating superscalar processor performance from traces

Lee, Kiyeon; Evans, Shayne; Cho, Sangyeun

doi:10.1109/ispass.2009.4919655

Cited by 18 publications

(22 citation statements)

References 26 publications

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“…The detailed mode is based on the Reorder-Buffer Occupancy Analysis model proposed by Lee et al [21]. When running in detailed mode, TaskSim models a user-defined memory hierarchy including private and shared cache memories, interconnect structures and DRAM.…”

Section: Methodsmentioning

confidence: 99%

TaskPoint: Sampled simulation of task-based programs

Grass

Rico

Casas

et al. 2016

2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Sampled simulation is a mature technique for reducing simulation time of single-threaded programs, but it is not directly applicable to simulation of multi-threaded architectures. Recent multi-threaded sampling techniques assume that the workload assigned to each thread does not change across multiple executions of a program. This assumption does not hold for dynamically scheduled task-based programming models. Taskbased programming models allow the programmer to specify program segments as tasks which are instantiated many times and scheduled dynamically to available threads. Due to system noise and variation in scheduling decisions, two consecutive executions on the same machine typically result in different instruction streams processed by each thread.In this paper, we propose TaskPoint, a sampled simulation technique for dynamically scheduled task-based programs. We leverage task instances as sampling units and simulate only a fraction of all task instances in detail. Between detailed simulation intervals we employ a novel fast-forward mechanism for dynamically scheduled programs. We evaluate the proposed technique on a set of 19 task-based parallel benchmarks and two different architectures. Compared to detailed simulation, TaskPoint accelerates architectural simulation with 64 simulated threads by an average factor of 19.1 at an average error of 1.8% and a maximum error of 15.0%.

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Section: Methodsmentioning

confidence: 99%

TaskPoint: Sampled simulation of task-based programs

Grass

Rico

Casas

et al. 2016

2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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“…Several approximate microarchitecture simulation methods have been proposed [3], [8], [9], [10], [11], [2], [12], [13] (the list is not exhaustive). In general, these methods trade accuracy for simulation speed.…”

Section: Approximate Simulationmentioning

confidence: 99%

Selecting benchmark combinations for the evaluation of multicore throughput

Velásquez

Michaud

Seznec

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Most high-performance processors today are able to execute multiple threads of execution simultaneously. Threads share processor resources, like the last-level cache, which may decrease throughput in a non obvious way, depending on threads' characteristics. Computer architects usually study multiprogrammed workloads by considering a set of benchmarks and some combinations of these benchmarks. Because detailed microarchitecture simulators are slow, we want a subset of combinations that is as small as possible, yet representative. However, there is no standard method for selecting such sample, and different authors have used different methods. It is not clear how the choice of a particular sample impacts the conclusions of a study. We propose and compare different sampling methods for defining multiprogrammed workloads for computer architecture studies. We evaluate their effectiveness with a case study, the comparison of several multicore last-level cache replacement policies. We show that random sampling, the simplest method, is a possible way to define a representative workload sample, provided the sample is large enough. We propose a method for estimating the required sample size based on fast approximate simulation. We propose a new method, workload stratification, which is very effective at reducing the sample size in situations where random sampling would require large samples.

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“…Lee et al proposed and studied several behavioral core models [18], [1]. These models consist of a trace of L2 accesses annotated with some information, in particular timestamps, like in the ASPEN model.…”

Section: B Behavioral Core Modelsmentioning

confidence: 99%

“…Lee et al recently introduced the PDCM behavioral core model [1]. During the model building phase, a per-application trace is generated from a cycle-accurate microarchitecture simulator, assuming an ideal L2 cache, i.e., forcing an L2 cache hit on each L1 cache miss.…”

Section: The Pdcm Behavioral Modelmentioning

confidence: 99%

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BADCO: Behavioral Application-Dependent Superscalar Core model

Velásquez¹,

Michaud²,

Seznec³

2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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Abstract-Microarchitecture research and development rely heavily on simulators. The ideal simulator should be simple and easy to develop, it should be precise, accurate and very fast. But the ideal simulator does not exist, and microarchitects use different sorts of simulators at different stages of the development of a processor, depending on which is most important, accuracy or simulation speed. Approximate microarchitecture models, which trade accuracy for simulation speed, are very useful for research and design space exploration, provided the loss of accuracy remains acceptable. Behavioral superscalar core modeling is a possible way to trade accuracy for simulation speed in situations where the focus of the study is not the core itself. In this approach, a superscalar core is viewed as a black box emitting requests to the uncore at certain times. A behavioral core model can be connected to a cycle-accurate uncore model. Behavioral core models are built from cycle-accurate simulations. Once the time to build the model is amortized, important simulation speedups can be obtained. We describe and study a new method for defining behavioral models for modern superscalar cores. The proposed Behavioral Application-Dependent Superscalar Core model, BADCO, predicts the execution time of a thread running on a superscalar core with an error less than 10 % in most cases. We show that BADCO is qualitatively accurate, being able to predict how performance changes when we change the uncore. The simulation speedups we obtained are typically between one and two orders of magnitude.

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Accurately approximating superscalar processor performance from traces

Cited by 18 publications

References 26 publications

TaskPoint: Sampled simulation of task-based programs

TaskPoint: Sampled simulation of task-based programs

Selecting benchmark combinations for the evaluation of multicore throughput

BADCO: Behavioral Application-Dependent Superscalar Core model

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