An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor

Oh, Taecheol; Lee, Hyunjin; Lee, Kiyeon; Cho, Sangyeun

doi:10.1109/isvlsi.2009.27

Cited by 23 publications

(15 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Huh et al [8] studied area and performance trade-offs. Oh et al [13] developed analytical models of various cache organizations. Cassidy and Andreou [2] introduced a closed form solution to optimally allocate constrained area between core and cache in a symmetric CMP.…”

Section: Introductionmentioning

confidence: 99%

Cache Hierarchy Optimization

Yavits

Morad

Ginosar

2014

IEEE Comput. Arch. Lett.

View full text Add to dashboard Cite

Power consumption, off-chip memory bandwidth, chip area and Network on Chip (NoC) capacity are among main chip resources limiting the scalability of Chip Multiprocessors (CMP). A closed form analytical solution for optimizing the CMP cache hierarchy and optimally allocating area among hierarchy levels under such constrained resources is developed. The optimization framework is extended by incorporating the impact of data sharing on cache miss rate. An analytical model for cache access time as a function of cache size is proposed and verified using CACTI simulation.

show abstract

Section: Introductionmentioning

confidence: 99%

Cache Hierarchy Optimization

Yavits

Morad

Ginosar

2014

IEEE Comput. Arch. Lett.

View full text Add to dashboard Cite

show abstract

“…In this paper, we perform a similar study in the context of multi-threaded PDES. Several studies focused on developing analytical models for the core, cache and on-chip interconnect area [1,26,33,19]. The cache subsystem design has also been studied in great detail.…”

Section: Related Workmentioning

confidence: 99%

“…The work of [35] evaluated the impact of CMP cache sharing on multi-threaded applications and demonstrated benefits of cache-sharing aware program transformations. Oh et al [26] and Wentzlaff [33] proposed simple analytical models to study trade-offs between the core count and the cache capacity under finite die area. Analytical models for thermal implications of CMP designs [24] and its impact on network scalability [4] have also been developed.…”

Section: Related Workmentioning

confidence: 99%

Exploring many-core architecture design space for parallel discrete event simulation

Zhang

Wang

Ponomarev

et al. 2014

Proceedings of the 2nd ACM SIGSIM Conference on Principles of Advanced Discrete Simulation

View full text Add to dashboard Cite

As multicore and manycore processor architectures are emerging and the core counts per chip continue to increase, it is important to evaluate and understand the performance and scalability of Parallel Discrete Event Simulation (PDES) on these platforms. Most existing architectures are still limited to a modest number of cores, feature simple designs and do not exhibit heterogeneity, making it impossible to perform comprehensive analysis and evaluations of PDES on these platforms. Instead, in this paper we evaluate PDES using a full-system cycle-accurate simulator of a multicore processor and memory subsystem. With this approach, it is possible to flexibly configure the simulator and perform exploration of the impact of architecture design choices on the performance of PDES. In particular, we answer the following four questions with respect to PDES performance and scalability: (1) For the same total chip area, what is the best design point in terms of the number of cores and the size of the on-chip cache? (2) What is the impact of using in-order vs. out-of-order cores? (3) What is the impact of a heterogeneous system with a mix of in-order and out-oforder cores? (4) What is the impact of object partitioning on PDES performance in heterogeneous systems? To answer these questions, we use MARSSx86 simulator for evaluating performance, and rely on Cacti and McPAT tools to derive the area and latency estimates for cores and caches.

show abstract

“…Oh et al [35] presented an analytical model to study the trade-off of the core count and the cache capacity in a CMP under area constraint. Alameldeen et al [2] used analytical modeling to study the number of CMP cores vs. cache size.…”

Section: Related Workmentioning

confidence: 99%

“…Each workload task is characterized by miss rates defined in [5] using PARSEC [10] and NAS [11], corresponding to the sequential-parallel synchronization data exchange. Further, we have applied assumptions similar to those used in [5], [20] and [35] for the constants described in (23) - (25). Our framework finds the optimal resource allocation in a broad spectrum of constraints.…”

Section: Convex Optimizationmentioning

confidence: 99%

Convex optimization of resource allocation in asymmetric and heterogeneous SoC

Morad

Yavits

Ginosar

2014

2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

View full text Add to dashboard Cite

Chip area, power consumption, execution time, off chip memory bandwidth, overall cache miss rate and Network on Chip (NoC) capacity are limiting the scalability of SoCs. Consider a workload comprising a sequential and multiple concurrent tasks and asymmetric or heterogeneous SoC architecture. A convex optimization framework is proposed, for selecting the optimal set of processing cores and allocating area and power resources among them, the NoC and the last level cache, under constrained total area, total average power, total execution time and off-chip bandwidth. The framework relies on analytical performance and power models of the processing cores, NoC and last level cache as a function of their allocated resources. Due to practical implementation of the cores, the optimal architecture under constraints may exclude several of the cores. Several asymmetric and heterogeneous configurations are explored. Convex optimization is shown to extend optimizations based on Lagrange multipliers. We find that our framework obtains the optimal chip resources allocation over a wide spectrum of parameters and constraints, and thus can automate complex architectural design, analysis and verification.

show abstract

An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor

Cited by 23 publications

References 12 publications

Cache Hierarchy Optimization

Cache Hierarchy Optimization

Exploring many-core architecture design space for parallel discrete event simulation

Convex optimization of resource allocation in asymmetric and heterogeneous SoC

Contact Info

Product

Resources

About