Two‐phase trace‐driven simulation (TPTS): a fast multicore processor architecture simulation approach

Abstract

Simulation is indispensable in computer architecture research. Researchers increasingly resort to detailed architecture simulators to identify performance bottlenecks, analyze interactions among different hardware and software components, and measure the impact of new design ideas on the system performance. However, the slow speed of conventional execution‐driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper describes a novel fast multicore processor architecture simulation framework called Two‐Phase Trace‐driven Simulation (TPTS), which splits detailed timing simulation into a trace generation phase and a trace simulation phase. Much of the simulation overhead caused by uninteresting architectural events is only incurred once during the cycle‐accurate simulation‐based trace generation phase and can be omitted in the repeated trace‐driven simulations. We report our experiences with tsim, an event‐driven multicore processor architecture simulator that models detailed memory hierarchy, interconnect, and coherence protocol based on the TPTS framework. By applying aggressive event filtering, tsim achieves an impressive simulation speed of 146 millions of simulated instructions per second, when running 16‐thread parallel applications. Copyright © 2010 John Wiley & Sons, Ltd.

CloudCache: Expanding and shrinking private caches

“…We evaluate CloudCache with a detailed trace-driven CMP architecture simulator [25]. The parameters of the machine we model are given in Table 2.…”

Virtual platforms: Breaking new grounds

“…Addressing the trade-off between performance and accuracy, trace-driven simulations accelerate the design space exploration by eliminating unnecessary details in the models [5,6]. The idea behind this method is to capture and abstract the behavior of processing elements in the form of application traces.…”

On the simulation of large-scale architectures using multiple application abstraction levels

“…This kind of representation was widely used by trace memory simulation methods [Black et al 1996;Uhlig and Mudge 1997] that benefited from trace reduction techniques (e.g., trace stripping [Puzak 1985;Wang and Baer 1990]) to speed up simulation. More recently, some works [Lee et al 2009;Lee et al 2010] have proposed simulation techniques to accurately simulate the performance of in-order and out-of-order cores using memory access traces at this level of application abstraction.…”

“…This simple extension allows accurate simulation of multi-core architectures using scratchpad memories, based on the fact that the computation on processing elements working on such local memories is independent of external events. Additionally, an intermediate level of abstraction incorporates traditional techniques from trace memory simulation [Uhlig and Mudge 1997;Lee et al 2010] to provide fast and accurate simulation of the memory system.…”