On the simulation of large-scale architectures using multiple application abstraction levels

Rico, Alejandro; Cabarcas, Felipe; Villavieja, Carlos; Pavlovic, Milan; Vega, Augusto; Etsion, Yoav; Ramírez, Alex; Valero, Mateo

doi:10.1145/2086696.2086715

Cited by 51 publications

(60 citation statements)

References 43 publications

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“…Given that our simulated caches are going to have a larger size than the trace filter caches, we are certain that at least the same number of memory accesses will reach the main memory, as with unfiltered traces. This method has been previously applied in the work of Rico et al [14] resulting with trace size reductions of up to 98%.…”

Section: Discussionmentioning

confidence: 99%

Data placement in HPC architectures with heterogeneous off-chip memory

Pavlovic

Puzovic

Ramírez

2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

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Abstract-The performance of HPC applications is often bounded by the underlying memory system's performance. The trend of increasing the number of cores on a chip imposes even higher memory bandwidth and capacity requirements. The limitations of traditional memory technologies are pushing research in the direction of hybrid memory systems that, besides DRAM, include one or more modules based on some of the higherdensity non-volatile memory technologies, where one of them will provide the required bandwidth, while the other will provide the required capacity for the application. This creates many challenges with data placement and migration policies between the modules of such hybrid memory system. In this paper, we propose an architecture with a hybrid memory design that places two technologically different memory modules in a flat address space. On such system, we evaluate several HPC workloads against different data placement and migration policies, compare their performance by means of execution time and the number of non-volatile memory writes, and consider how it can be applied to the future HPC architectures. Our results show that the hybrid memory system with dynamic page migration and limited DRAM capacity, can achieve performance that is comparable to a hypothetical, hard to implement, DRAM-only system.

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Section: Discussionmentioning

confidence: 99%

Data placement in HPC architectures with heterogeneous off-chip memory

Pavlovic

Puzovic

Ramírez

2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

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“…The TaskSim Simulator: We evaluate our methodology using the TaskSim simulator [19,20]. TaskSim is a cycleaccurate, trace-driven performance simulator for multi-core architectures.…”

Section: Methodsmentioning

confidence: 99%

TaskPoint: Sampled simulation of task-based programs

Grass

Rico

Casas

et al. 2016

2016 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Sampled simulation is a mature technique for reducing simulation time of single-threaded programs, but it is not directly applicable to simulation of multi-threaded architectures. Recent multi-threaded sampling techniques assume that the workload assigned to each thread does not change across multiple executions of a program. This assumption does not hold for dynamically scheduled task-based programming models. Taskbased programming models allow the programmer to specify program segments as tasks which are instantiated many times and scheduled dynamically to available threads. Due to system noise and variation in scheduling decisions, two consecutive executions on the same machine typically result in different instruction streams processed by each thread.In this paper, we propose TaskPoint, a sampled simulation technique for dynamically scheduled task-based programs. We leverage task instances as sampling units and simulate only a fraction of all task instances in detail. Between detailed simulation intervals we employ a novel fast-forward mechanism for dynamically scheduled programs. We evaluate the proposed technique on a set of 19 task-based parallel benchmarks and two different architectures. Compared to detailed simulation, TaskPoint accelerates architectural simulation with 64 simulated threads by an average factor of 19.1 at an average error of 1.8% and a maximum error of 15.0%.

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“…We use TaskSim [22], a trace-driven [21] computer architecture simulator that simulates applications written in data-flow task-based programming models. The simulated system is a 4-core processor with a cache hierarchy consisting of 3 levels, two of which are private, L1 (4-way, 32 KB) and L2 (8-way, 256 KB), and the LLC is shared (16- …”

Section: Simulation Infrastructurementioning

confidence: 99%

Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals

Dimić

Moretó

Casas

et al. 2017

Lecture Notes in Computer Science

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Abstract. Processor speed is improving at a faster rate than the speed of main memory, which makes memory accesses increasingly expensive. One way to solve this problem is to reduce miss ratio of the processor's last level cache by improving its replacement policy. We approach the problem by co-designing the runtime system and hardware and exploiting the semantics of the applications written in data-flow task-based programming models to provide hardware with information about the task types and task data-dependencies. We propose the Task-Type aware Insertion Policy, TTIP, which uses the runtime system to dynamically determine the best probability per task type for bimodal insertion in the recency stack and the static Dependency-Type aware Insertion Policy, DTIP, that inserts cache lines in the optimal position taking into account the dependency types of the current task. TTIP and DTIP perform similarly or better than state-of-the-art replacement policies, while requiring less hardware.

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On the simulation of large-scale architectures using multiple application abstraction levels

Cited by 51 publications

References 43 publications

Data placement in HPC architectures with heterogeneous off-chip memory

Data placement in HPC architectures with heterogeneous off-chip memory

TaskPoint: Sampled simulation of task-based programs

Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals

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