No abstract

No abstract

No abstract

No abstract

The trend towards low cost integration of wireless systems has driven the introduction of innovative single chip radio architectures in CMOS technologies as an inexpensive alternative to the traditional superheterodyne bipolar implementations. This work describes a 0.18µm CMOS direct conversion transceiver, part of a two-chip solution implementing both PHY and MAC for 802.11a.Although attractive as a highly integrated solution, direct conversion architecture suffers from problems such as DC offsets, flicker noise and poor quadrature matching, that are further aggravated by using CMOS technology [1]. Furthermore, the 802.11a standard high bit-rate modes require closely matched I/Q frequency response. To alleviate those limitations, a transceiver topology allowing the use of the companion digital chip for calibration, has been implemented as shown in Fig. 20.2.1. Both transmitter and receiver use direct conversion and employ fully differential signal paths. By adding loop-back switches, the DC offset, TX and RX I/Q gain mismatch and I/Q frequency response can be independently calculated and corrected during the idle time between frames or at power-up.The balanced low noise amplifier (LNA) shown in Fig. 20.2.2 uses an NMOS cascoded differential pair with inductive degeneration. On-chip spiral inductors are used, except for the input matching network, which uses bond-wire inductors. Two gain settings of 16dB/10dB are provided. At the high gain setting, the LNA has a noise figure of 3.2dB. Input matching is wideband, to cover all three 802.11a bands. The output of the LNA is demodulated directly into baseband by a quadrature demodulator, based on the mixer shown in Fig. 20.2.2. A folded current signal path using PMOS switches reduces flicker noise. The mixer features 10dB of gain and a noise figure of less than 12dB. The overall receive chain path DC offset is calculated, tracked digitally, and real-time corrected at the output of the RX mixers by two independent 8-bit current steering digital-to-analog converters (DACs).The baseband path of the receiver consists of two programmable gain amplifiers (PGA), a low-pass filter and an output buffer. The first PGA employs a low-noise, high dynamic range single-stage amplifier, while the second is an operational amplifier-based feedback gain stage. The composite gain varies from 2dB to 53dB, programmable in 3dB steps. The fourth-order Chebyschev filter cell used for channel selection is implemented as a cascade of two biquads. It employs Gm-OTA-C integrators based on the regulated cascode topology, as shown in Fig. 20.2.3 and is tuned by the DC voltage Vc generated by an 8-bit DAC. During transceiver calibration, the responses of both I and Q paths are independently measured and corrected. I-path is measured from the feedback path formed by switches SW5-SW1, while Q-path is from SW5-SW2. A calibration sequence generated digitally is used to set the bandwidth to 9MHz. Residual mismatch along the pass-band of the filters is measured and compensated digitally. The output of the...