The growing occurrences of WLAN, BT, and FM on the same mobile device have created a demand for putting all three on the same die to save on die size, I/O count, BOM, and ultimately cost. Common blocks such as crystal oscillator, bandgap, and power management units can be easily shared. This paper presents a solution in which 802.11a/b/g WLAN, single-stream 11n (SSN) WLAN, BT, and FM subsystem and radio are integrated on a single die. Figure 25.3.1 shows a block diagram of the SOC. The radio supports 802.11a/b/g, SSN, EDR BT, and FM receiver. Crystal oscillator, low-power oscillator, RCAL, bandgap, and PMU are all shared between the different radios. The shared logic block decides which radio should get the control of the shared analog blocks in conjunction with the co-existence algorithm. In the 2.4GHz receive path, a Shared LNA (SLNA) is used to receive both WLAN and BT signals. The SLNA drives both WLAN LNA2 and BT LNA. Current-mode signaling is used to maintain signal integrity over long routing channels since the rest of the BT core resides a few millimeters away. The two-stage LNA receive architecture helps maintain optimum cascaded noise performance over slow PVT corners. For the WLAN receiver, single-weight combiners (SWC) are implemented using signalpath cartesian phase-shifters to improve receive sensitivity by 3dB by using an additional antenna [1]. In the transmit path, the BT transmitter has the option to use either the WLAN path for output power up to 20dBm or its low-power legacy BT path for better efficiency. The WLAN 2.4GHz load of the mixer serves as the load for the BT mixer output. Two cascaded common-gate stages are employed to pass the BT transmit signal into the WLAN transmit path. The cascaded common-gate stage enables the 2.4GHz BT Tx signal to be routed over long distance and ensures good reverse isolation. Additional shunt and series switches close to the tapping points are used to minimize the loading effect and increase isolation when both WLAN and BT are transmitting at the same time using separate PAs.To remove the need for external baluns, both SLNA and PA use on-chip transformers to convert differential signals to 50 ohms single-ended. The SLNA uses a common-gate input stage with cross-coupled capacitors for wideband matching and noise cancellation [2]. By utilizing the on-chip transformer, two AC coupling capacitors and two shunt inductors can be removed. The SLNA achieves gain of 26dB, noise figure of 3.5dB, and IIP3 of -2dBm all including loss of the transformer. The PA is a pseudo-differential common-source amplifier with transformer as its load. Tuning capacitors at the load are used to match the PA for maximum power and efficiency [3]. For the input stage, core NMOS transistors are used to get the maximum current gain at the input stage. High-voltage NMOS devices are used for the cascode devices to handle the very large voltage swings at its drain. Care must be given to make sure that the input devices are not subject to higher voltages at their drains than they can handle. ...
