No abstract

No abstract

In this paper, we report our experimental study on electron mobility in silicon gate-all-around (GAA) nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) on (100)-oriented silicon-on-insulator (SOI) substrates. With the aim of accurate mobility measurement, the improved split capacitance-voltage (C-V ) method is utilized to remove parasitic resistance and capacitance. Accurate electron mobility in [100]-directed nanowires is achieved for the first time and shows high electron mobility that approaches the (100) bulk universal curve, while electron mobility in [110]-directed nanowires shows large degradation from the universal curve. The underlying physical mechanisms of mobility behaviors in nanowires on (100)-oriented SOI substrates are also investigated.

The equation governing nonlinear two-dimensional interchange modes is derived and an exact solution consisting of an infnite chain of'solitons is found. It is suggested that soliton chains of interchange modes in plasmas could be observed experimentally.'

No abstract

A special device-matrix-array (DMA) TEG of 16k bit SRAM cells has been designed. Static noise margins (SNM) and 6 transistors in cells are directly measured and their fluctuations are examined. It is found for the first time that one-side SNM follows the normal distribution up to ±4σ. It is also found that the cell stability is worse than circuit simulation using V th of measured 6 transistors. Furthermore, the post-fabrication self-convergence scheme by NBTI stress is applied to DMA SRAM TEG and the cell stability improvement is demonstrated experimentally for the first time.Introduction The instability in SRAM cells due to transistor variability is one of the most critical issues in recent VLSI [1][2][3][4][5][6][7]. The yield and minimum operating voltage (V min ) are mainly determined by SRAM cells, and therefore, the analysis of cell unbalances at transistor level is essential for better understanding of SRAM stability. However, it was impossible to measure a number of individual transistors and SNM in SRAM cell array. Moreover, circuit simulation results on SNM or V min are not necessarily consistent with measured data [7].In this work, 16k bit DMA TEG for SRAM cell array is designed, and cell stability and individual transistors are directly measured in order to investigate mechanisms of cell unbalances. Circuit simulation of SNM is performed using measured V th of individual transistors and compared with measured SNM. It is found that the simulation overestimate cell stability. Moreover, the advantage of the post-fabrication self-convergence technique we have proposed [8] is validated by DMA SRAM TEG.DMA TEG for SRAM The 16k bit DMA TEG is based on the 1M DMA TEG we have developed [9]. DUT is replaced by SRAM mini-array of 6x8 cells. Terminals of V dd , Gnd, WL, BLL, BLR as well as two storage nodes (VL, VR) at the center cell can be accessed ( Fig. 1), and SNM and individual 6 transistors can be measured. Fig. 2 shows measured V th of PMOS, driver NMOS, and access NMOS in the linear region. Normal distributions of V th of individual transistors are confirmed.Measurements of SNM Fig. 3 shows measured SNM of 16k bit cells. SNM is defined by the smaller one of left and right SNMs (SNM(L) and SNM(R)). Although SNM is deviated from the normal distribution, it is found that both SNM(L) and SNM(R) follows normal distribution up to ±4σ. This is a useful result for prediction of cell stability at very large scale SRAM.Measured V dd dependence of SNM is depicted in Fig. 4, showing rapid degradation of SNM at lower V dd . Fig. 5 shows correlation between SNM at 1.2V and SNM at lower V dd . It should be noted that there is a poor correlation between SNMs at 1.2V and 0.4V. Even if two cells have the same SNM at 1.2V, one cell fails at 0.4V and another cell does not (Figs. 6, 7). Each cell exhibits very different V dd dependence (Fig. 8).In order to examine the cell unbalance in more detail, cells with SNM between 0.20V and 0.21V are selected (Fig. 5). It is found that SNM at smaller V dd of selected cells is closely ...

No abstract

Electron mobility in ultrathin body MOSFETs in double-gate (DG) operation has been investigated with SOI thickness of less than 4 nm for the first time. Although mobility degradation in DG compared to single gate occurs with SOI thickness of larger than 2 nm, the degradation is suppressed with SOI thickness of 1.7 nm. This suppression mechanism is explained by strong quantum confinement effect by an extremely thin SOI layer.Index Terms-Double gate (DG), electron mobility, MOSFET, SOI.