Electron Mobility in Silicon Gate-All-Around [100]- and [110]-Directed Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor on (100)-Oriented Silicon-on-Insulator Substrate Extracted by Improved Split Capacitance–Voltage Method

Chen, Jiezhi; Saraya, Takura; Miyaji, Kagami; Shimizu, K.; Hiramoto, Toshiro

doi:10.1143/jjap.48.011205

Cited by 24 publications

(24 citation statements)

References 17 publications

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“…[1][2][3][4][5][6][7] The future may see the use of threedimensional (3D) MOSFETs, such as vertically stacked SiNW FETs, [8][9][10][11][12] for high device densities. An asymmetric channel structure is expected for the vertically stacked SiNW FETs because of the fabrication processes.…”

mentioning

confidence: 99%

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Sato

Kakushima

Ohmori

et al. 2011

Applied Physics Letters

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This letter reports the electrical characteristics of nonuniform silicon nanowire nFETs with asymmetric source and drain widths. For electrostatic properties, reduced drain-induced barrier lowering (DIBL) is achieved in a device in which the source is wider than the drain. For carrier transport properties, higher values of surface-roughness-limited mobility (l SR ) are obtained in the sample with the wider drain size. Our electrostatic model shows that the concentration of lines of electric force is relaxed near the wider source edge, which results in smaller DIBL. The asymmetric l SR is attributed to the channel surface morphology with (110)-and (100)-faceted surfaces.

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confidence: 99%

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Sato

Kakushima

Ohmori

et al. 2011

Applied Physics Letters

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“…We have evaluated inversion charge density and effective carrier mobility focusing on the upper-corner angle of SiNW channels. However, it has also been reported that effective carrier mobility is also influenced by the size of cross-section [14]. We will demonstrate that the upper-corner angle of the SiNW channel has more important roles on the electrical characteristics of SiNW FET in the discussion section.…”

Section: Methodsmentioning

confidence: 69%

“…As a result, there exist various cross-sectional shapes of the SiNW channels: triangular [2,4], circular [1], ellipsoidal [9], and rectangular [10]. The effects of the various cross-sectional shapes of the SiNW FETs on their electrical properties have been reported, for example, the gate capacitance [11], the on-current I ON [12], the threshold voltage (V th ) [13], the effective carrier mobility (µ eff ) [14], and the interfacial state density (D it ) [15].…”

Section: Introductionmentioning

confidence: 99%

Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure

Sato

Kakushima

Ahmet

et al. 2011

Solid-State Electronics

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Structural effects, especially corner angle of upper-corners of trapezoidal and rectangular, and triangular cross-sectional shapes of silicon nanowire field-effect transistors on effective carrier mobility and normalized inversion charge density have been investigated. <100>-directed silicon nanowire field-effect transistors with semi-gate around structure fabricated on (100)-oriented silicon-on-insulator wafers were evaluated. As the upper-corner angle decreased from obtuse to acute angle, we observed an increased amount of inversion charge using split-CV measurement. On the other hand, the effective carrier mobility dependence on the upper-corner angle seems to have an optimized point near 100 o at 296 K. Although normalized inversion charge density was the largest with acute angles, effective carrier mobility with acute upper-corner angle was severely degraded.Considering the intrinsic delay time of SiNW FET, SiNW FETs with trapezoidal cross-section with upper-corner angle of 100 o is more suitable in this work to achieve high electrical performance. We believe these findings could represent guidelines for the design of high-performance SiNW FETs.

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“…[36][37][38] To remove the effects of parasitic capacitance and resistance (R p ) in MOSFETs, mobility estimations are performed by the split C-V method combined with the double L eff method, 38 that is, devices of different lengths are compared to remove parasitic effects as mentioned in foresaid parts. [36][37][38] To remove the effects of parasitic capacitance and resistance (R p ) in MOSFETs, mobility estimations are performed by the split C-V method combined with the double L eff method, 38 that is, devices of different lengths are compared to remove parasitic effects as mentioned in foresaid parts.…”

Section: Demonstration Of Read/write Operation and Detailedmentioning

confidence: 99%

Spin-Based MOSFET and Its Applications

Saito

Inokuchi

Ishikawa

et al. 2011

J. Electrochem. Soc.

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We developed a novel spintronic device "Spin-transfer-Torque Switching-MOSFET (STS-MOSFET)" which offers non-volatile memory and transistor functions that are CMOS compatible and have high endurance and a fast write time. STS-MOSFETs with Heusler alloy (Co 2 FeAl 0.5 Si 0.5 ) were prepared and reconfigurability of the novel spintronics-based STS-MOSFET was successfully realized in the transport properties. The transistor properties such as drain current as a function of drain voltage, sub-threshold and carrier mobility properties are not hindered by ferromagnet/tunnel source/drain electrodes. The device showed clear magnetocurrent (MC) and write characteristics with the endurance of over 10 5 cycles. Moreover, the area and speed of million-gate spin field programmable gate arrays (FPGAs) are numerically benchmarked with CMOS FPGA for 22, 32, and 45 nm technologies including a 20% transistor size variation. We showed that the performance of spin FPGA becomes superior to that of conventional CMOS FPGA as transistor size decreases and MC ratio increases. The overall properties of the STS-MOSFETs show great potentialities for future reconfigurable integrated circuits based on CMOS technology. Device Fabrication and ExperimentsThe spin injection devices and back-gate STS-MOSFETs with MTJs were fabricated on Si (001) and p-type Si-on-Insulator (SOI) substrates. We used a heavily doped n-type Si surface (nþ-Si) under the tunnel barrier (I)/FM electrodes to reduce interfacial resistance. The regions for n-type channels and nþ-Si were formed in the Si substrate by using ion implantation of phosphorus (P) and arsenic (As), respectively, and post-rapid thermal annealing. We are confining spin transport in the active region of the n-type channel. The

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Electron Mobility in Silicon Gate-All-Around [100]- and [110]-Directed Nanowire Metal–Oxide–Semiconductor Field-Effect Transistor on (100)-Oriented Silicon-on-Insulator Substrate Extracted by Improved Split Capacitance–Voltage Method

Cited by 24 publications

References 17 publications

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Electrical characteristics of asymmetrical silicon nanowire field-effect transistors

Effects of corner angle of trapezoidal and triangular channel cross-sections on electrical performance of silicon nanowire field-effect transistors with semi gate-around structure

Spin-Based MOSFET and Its Applications

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