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This paper presents a fully synthesizable successive-approximation-register (SAR) analog-todigital converter (ADC) for on-chip distributed waveform monitoring in a low-power system-on-chip (SoC). All blocks in the proposed ADC are designed using only standard digital cells, enabling an auto-generation based on regular digital design tools. Therefore, the proposed ADC provides enhanced portability and reusability which facilitate integration into various functional blocks requiring testing and diagnosis. To implement the SAR ADC, a synthesizable voltage digital-to-analog converter (VDAC) and a rail-torail hybrid comparator are proposed in this paper. An inherited nonlinearity of the standard-cell-based VDAC is compensated by a histogram-based soft calibration which can be easily embedded in a waveform reconstruction module. In addition, an oversampling technique with a redundant error correction method is employed to realize the fully synthesizable design without a sample-and-hold (S/H) circuit. The proposed ADC was fabricated in 28-nm CMOS technology, occupying an active area of 0.002 mm 2. The ADC achieves 5.39-bit effective-number-of-bit (ENOB) at 500-kS/s sampling rate. The power consumption of the ADC is 92.2 µW with a supply voltage of 0.5 V.

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We present the hybrid-integrated silicon photonic receiver and transmitter based on silicon photonic devices and 65 nm bulk CMOS interface circuits operating over 30 Gb/s with a 10(-12) bit error rate (BER) for λ ~1550nm. The silicon photonic receiver, operating up to 36 Gb/s, is based on a vertical-illumination type Ge-on-Si photodetector (Ge PD) hybrid-integrated with a CMOS receiver front-end circuit (CMOS Rx IC), and exhibits high sensitivities of -11 dBm, -8 dBm, and -2 dBm for data rates of 25 Gb/s, 30 Gb/s and 36 Gb/s, respectively, at a BER of 10(-12). The measured energy efficiency of the Si-photonic receiver is 2.6 pJ/bit at 25 Gb/s with an optical input power of -11 dBm, and 2.1 pJ/bit at 36 Gb/s with an optical power of -2 dBm. The hybrid-integrated silicon photonic transmitter, comprised of a depletion-type Mach-Zehnder modulator (MZM) and a CMOS driver circuit (CMOS Tx IC), shows better than 5.7 dB extinction ratio (ER) for 25 Gb/s, and 3 dB ER for 36 Gb/s. The silicon photonic transmitter achieves the data transmission with less than 10(-15) BER at 25 Gb/s, 10(-14) BER at 28 Gb/s, and 6 x 10(-13) BER with the energy efficiency of ~6 pJ/bit at 30 Gb/s.

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