2017
DOI: 10.1109/tcsii.2017.2753841
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A 0.4-to-1 V Voltage Scalable $\Delta \Sigma $ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS

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Cited by 21 publications
(6 citation statements)
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“…As shown in Table 4 , the listed devices [ 19 , 23 , 24 ] are the closest designs in terms of FoM to the proposed ADC. The main distinguishing factor of this work is the high dynamic range, since it uses the noise cancellation logic to suppress in-band noise.…”
Section: Resultsmentioning
confidence: 99%
“…As shown in Table 4 , the listed devices [ 19 , 23 , 24 ] are the closest designs in terms of FoM to the proposed ADC. The main distinguishing factor of this work is the high dynamic range, since it uses the noise cancellation logic to suppress in-band noise.…”
Section: Resultsmentioning
confidence: 99%
“…Literature offers several solutions, in [65] A 0.4-to-1 V Voltage Scalable ADC with Two-Step Hybrid Integrator in 65 nm CMOS is presented. Such devices present a scalable power consumption and bandwidth with maintaining an SNDR higher than 60dB.…”
Section: F Analog To Digital Conversionmentioning
confidence: 99%
“…Complex timing control logic must also be employed to properly share the op-amps among different stages. Alternative techniques attempt to replace the op-amps with other blocks, such as zero-crossing detectors [3], [4], dynamic-comparators [5], and inverters [6]. modulators with zero-crossing detectors can hardly achieve high resolution due to the voltage overshoots caused by delays from the zero-crossing event to the stable detection result generated, while the accuracy of modulators employing comparator-based and inverter-based integrators is mainly impaired by their limited dc gain and input-referred offset.…”
Section: Introductionmentioning
confidence: 99%