A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS

Hwang, Young‐Ha; Song, Yoonho; Park, Jun-Eun; Jeong, Deog‐Kyoon

doi:10.1109/asscc.2018.8579290

Cited by 18 publications

(9 citation statements)

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“…The mismatch in the CDAC can affect the ADC linearity, and the DEM technique can be used to address the issue [ 9 , 10 , 19 ]. Either random or cyclic selection can realize the DEM.…”

Section: Measured Resultsmentioning

confidence: 99%

“…Therefore, direct comparison is difficult. The DEM technique addresses the mismatch problem [ 9 , 19 ]. These works show slightly better FOM S than ours, while our work achieves better FOM W .…”

Section: Measured Resultsmentioning

confidence: 99%

“…These works show slightly better FOM S than ours, while our work achieves better FOM W . The work [ 19 ] uses the passive noise shaping filter; however, the comparator having three input branches increases the power and noise. Works [ 16 , 17 , 18 , 19 , 20 ] consume power > 100 μW, and it is difficult to use these works for the IoT demanding an ultra-low power.…”

Section: Measured Resultsmentioning

confidence: 99%

“…The noise shaping technique has been actively investigated to address the challenge [ 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 ]. This technique moves the in-band quantization noise from the signal band to out-of-band for improved signal-to-noise ratio (SNR).…”

Section: Introductionmentioning

confidence: 99%

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An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

Choi

Lee

2022

Sensors

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Herein, we present a noise shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) with an embedded passive gain multiplication technique. The noise shaping moves the in-band quantization noise from the signal band to out-of-band for improved signal-to-noise ratio (SNR). The proposed approach tackles the drawback of the previous active noise shaping (increased power and extra noise) and passive noise shaping (limited noise suppression and signal loss). Both noise shaping and gain multiplication are realized on-chip in an energy-efficient manner without an opamp. This approach uses only capacitors and switches in the finite impulse response (FIR) and infinite impulse response (IIR) filters. A comparator suppressing kickback noise is presented to handle the tradeoff between noise suppression and the filter capacitor size. The energy-efficient merged-capacitor switching (MCS) technique is effectively combined with rail-to-rail swing comparator and thermometer-coded capacitor array, which reduces the settling error in the digital to analog converter (DAC). The process-induced mismatch effect in the capacitive DAC is investigated using a behavioral model of the ADC. Additionally, we propose dynamic element matching (DEM) for the thermometer-coded capacitor array. The ADC is fabricated using a 0.18 μm CMOS process in an area of 0.26 mm2. Consuming 4.1 μW, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 66.5 dB and a spurious-free dynamic range (SFDR) of 79.1 dB. The figure-of-merit (FoM) of the ADC is 11.8 fJ/conversion-step.

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“…The mismatch in the CDAC can affect the ADC linearity, and the DEM technique can be used to address the issue [ 9 , 10 , 19 ]. Either random or cyclic selection can realize the DEM.…”

Section: Measured Resultsmentioning

confidence: 99%

Section: Measured Resultsmentioning

confidence: 99%

Section: Measured Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

Choi

Lee

2022

Sensors

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“…As another solution for low-voltage operation, a noise-shaping (NS) successive approximation register (SAR) ADC is proposed in reference [73]. The NS SAR ADC is a cascade of integrators feedforward (CIFF) structure ADC, and includes a 2nd order passive loop filter, dynamic element matching (DEM) for 3bit MSB, and digital error correction (DEC) for digital output.…”

Section: Noise-shaping Sar Adc With Passive Filtermentioning

confidence: 99%

Discrete-time delta-sigma analog-to-digital converter using VCO-based quantizer for IoT applications

An¹

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Low-power systems are essential for Internet-of-Things (IoT) applications powered by harvested energy or batteries, such as wearable devices, structural health monitoring, industrial process monitoring, and personal health monitoring. Analog to digital converter (ADC) is an essential part of the IoT sensor interface and communication system that receives analog signals such as radio waves, light, sound, and biological signals. Depending on the purpose, the ADC is designed for the targets of low voltage operation, dynamic voltage scaling, and high resolution. The technology and supply voltage scaling caused by technological advances reduce voltage headroom and signal power, which makes it challenging to achieve high performance in analog circuit design. A voltagecontrolled oscillator (VCO) based ADC that processes analog information in the time domain can be desirable for technology and supply voltage scaling.However, the conventional VCO-based ADCs present challenges such as dynamic voltage scaling, process variation, narrow input range, and discretetime operation. For high-resolution ADC design, ΔΣ ADC began regaining its popularity as a research topic for high resolution. The discrete-time (DT) ΔΣ ADC effectively reduces two primary noise sources. They are quantization noise and kT/C noise. kT/C noise is more prominent than the quantization noise in high-resolution ADC. kT/C noise is inversely proportional to sampling capacitance and oversampling ratio (OSR). Therefore, high OSR and large capacitance reduce the kT/C noise. Generally, high OSR is preferred to the large capacitance, for the area and power efficiency. However, high-resolution ADC designs are limited in environments where a high OSR cannot be applied.

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Recent advances in the three processes of NS SAR ADC

Ren,

Gong,

Jiang

et al. 2024

AEU - International Journal of Electronics and Communications

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A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS

Cited by 18 publications

References 0 publications

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

Discrete-time delta-sigma analog-to-digital converter using VCO-based quantizer for IoT applications

Recent advances in the three processes of NS SAR ADC

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