A 0.5-V Fully Synthesizable SAR ADC for On-Chip Distributed Waveform Monitors

Abstract

This paper presents a fully synthesizable successive-approximation-register (SAR) analog-todigital converter (ADC) for on-chip distributed waveform monitoring in a low-power system-on-chip (SoC). All blocks in the proposed ADC are designed using only standard digital cells, enabling an auto-generation based on regular digital design tools. Therefore, the proposed ADC provides enhanced portability and reusability which facilitate integration into various functional blocks requiring testing and diagnosis. To implement the SAR ADC, a synthesizable voltage digital-to-analog converter (VDAC) and a rail-torail hybrid comparator are proposed in this paper. An inherited nonlinearity of the standard-cell-based VDAC is compensated by a histogram-based soft calibration which can be easily embedded in a waveform reconstruction module. In addition, an oversampling technique with a redundant error correction method is employed to realize the fully synthesizable design without a sample-and-hold (S/H) circuit. The proposed ADC was fabricated in 28-nm CMOS technology, occupying an active area of 0.002 mm 2. The ADC achieves 5.39-bit effective-number-of-bit (ENOB) at 500-kS/s sampling rate. The power consumption of the ADC is 92.2 µW with a supply voltage of 0.5 V.

Fully Synthesizable Low-Area Analogue-to-Digital Converters With Minimal Design Effort Based on the Dyadic Digital Pulse Modulation

“…6.7 bits (8 bits) in dynamic (static) conditions. Its operation at the maximum sample rate of 2.2kS/s leads to a power consumption of 0.94 µW, which is the lowest reported and 100× less than [15]. The kHz-range sampling frequency of the proposed ADCs is lower than other fully-synthesizable ADCs, and is well suited for a wide range of voltage and current sensing applications (see Section IVA).…”

“…The BUF logic threshold is set to V LT = V DD /2 under a supply voltage V DD via symmetric transistor sizing (see considerations on matching in Section IV). In turn, OUT BUF is the input of the successive approximation logic that is commonly encountered in general SAR ADCs [15]. The SAR logic generates a sequence of digital values that progressively converges to the input value in N SAR iterations.…”

“…Sigma-Delta ( ) MASH ADCs (e.g., [13]) achieve the highest resolution at relatively low sample rates, but require significant analog design in addition to their digital components. Mostly-digital successive approximation register (SAR) ADCs have also been demonstrated for lowarea and low-resolution targets, while achieving rail-to-rail input range [15], [16].…”

“…Operation of the proposed ADCs in the kS/s range makes them suitable for a wide range of applications where physical signals with kHz-range bandwidth need to be sensed, at the relatively low resolutions allowed by digital ADC architectures [9]- [15]. Compared to prior art, the proposed ADCs exhibit the lowest area and the highest resolution among mostly-and fully-digital ADCs to date, while being designed with fully-automated digital design flows.…”

Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers

“…An alternative approach [17][18][19][20][21][22][23][24][25][26][27] aims at the implementation of analog functions by digital means. Leveraging this concept, a VCO-based OTA [28] and a digital-based [15] OTA (DB-OTA), Figure 1f,g, have been recently proposed [13,16].…”