Sample preparation is an indispensable process to biochemical reactions. Original reactants are usually diluted to the solutions with desirable concentrations. Since the reactants, like infant's blood, DNA evidence collected from a crime scene, or costly reagents, are extremely valuable, the usage of reactant must be minimized in the sample preparation process. In this paper, we propose the first reactant minimization approach, REMIA, during sample preparation on digital microfluidic biochips (DMFBs). Given a target concentration, REMIA constructs a skewed mixing tree to guide the sample preparation process for reactant minimization. Experimental results demonstrate that REMIA can save about 31%~52% of reactant usage on average compared with three existing sample preparation methods. Besides, REMIA can be extended to tackle the sample preparation problem with multiple target concentrations, and the extended version also successfully decreases the reactant usage further.

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partition tends to produce better results. However, to the best of our knowledge, finding a good input partition in Roth-Karp decomposition has not been formally addressed in previous research. In this paper, we propose a new heuristics to solve this problem.Roth-Karp decomposition is a classical decomposition method.Because it can reduce the number of input variables of a function, it becomes one of the most popular techniques used in LUT-based FPGA technology mapping.However, the lambda set selection problem, which can dramatically affect the decomposition quality in Roth-Karp decomposition, has not been formally addressed before. In this paper, we propose a new heuristic-based algorithm to solve this problem.The experimental results show that our algorithm can efficiently produce outputs with better decomposition quality than that produced by other algorithms without using lambda set selection strategy.

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In shared SoC bus systems, arbiters are usually adopted to solve bus contentions with various kinds of arbitration algorithms. We propose an arbitration algorithm, RT_lottery, which is designed to meet both hard real-time and bandwidth requirements. For fast evaluation and exploration, we use high abstract-level models in our system simulation environment to generate parameters for our configurable arbiter. The experimental results show that RT_lottery can meet all hard real-time requirements and perform very well in bandwidth allocation. The results also show that RT_lottery outperforms several commonly-used arbitration algorithms today.

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Power dissipation has become a pressing issue of concern in the designs of most electronic system as fabrication processes enter even deeper submicron regions. More specifically, leakage power plays a dominant role in system power dissipation. An emerging circuit design style, the reconfigurable single-electron transistor (SET) array, has been proposed for continuing Moore's Law due to its ultra-low leakage power consumption. Recently, several works have been proposed to address the issues related to automated synthesis for the reconfigurable SET array. Nevertheless, all of those existing approaches consider mandatory fabrication constraints of SET array merely in late synthesis stages. In this article, we propose a synthesis algorithm, featuring input-variable ordering and dynamic product term ordering, for area minimization. The fabrication constraints are taken into account at every synthesis stage of proposed flow to guarantee better synthesis outcomes. We also develop a simulated annealing-based postprocess to find a proper phase assignment of each input variable for further area reduction. Experimental results show that our new methodology can achieve up to 29% area reduction as compared to existing state-of-the-art techniques.

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