Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping

Abstract

partition tends to produce better results. However, to the best of our knowledge, finding a good input partition in Roth-Karp decomposition has not been formally addressed in previous research. In this paper, we propose a new heuristics to solve this problem.Roth-Karp decomposition is a classical decomposition method.Because it can reduce the number of input variables of a function, it becomes one of the most popular techniques used in LUT-based FPGA technology mapping.However, the lambda set selection problem, which can dramatically affect the decomposition quality in Roth-Karp decomposition, has not been formally addressed before. In this paper, we propose a new heuristic-based algorithm to solve this problem.The experimental results show that our algorithm can efficiently produce outputs with better decomposition quality than that produced by other algorithms without using lambda set selection strategy.

A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs

“…Since enumeration is very expensive, it is not applicable for functions with many variables. Recently, a heuristic was proposed which directly constructs a BS of fixed size from the SOP representation of f [19]. In contrast to the approaches mentioned above, Schlichtmann proposed a BDD-based variable partitioning approach that also selects a good BS size [20].…”

Three parameters to find functional decompositions

“…Roughly speaking, decomposition methods can be classied into two: Exhaustive methods [2,8,9,14,16,18,20,22] and heuristic methods [3,5,23,11,12]. Exhaustive methods nd all possible decompositions, but they are usually time consuming.…”

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping

“…So we only apply this collapsing operation to small circuits with a limited number of PI's, for example, 10. Therefore, we develop an approach MIXED, which applies not only the modified chortle-crf algorithm but also a modified Roth-Karp decomposition algorithm [5][6] to such collapsed circuits. The results of our initial network generation are shown at column MIXED of Table I.…”

“…As we described before, some networks should be collapsed into the two-level form, then be decomposed by Roth-Karp decomposition to get the better mapping solutions. So, if the number of PI nodes of the selected partial network is under a predifined upper bound, it is first collapsed then decomposed by a modified Roth-Karp decomposition algorithm proposed in [5][6].…”

“…According to the objectives, they can be roughly classified into two categories: (1) Area Optimization [2][3][4][5][6]: These algorithms minimize the number of LUT's used to implement the given circuit based on the assumption that the number of LUT's in the FPGA design is a good measurement of the area of FPGA implementations. (2) Performance Optimization [7][8][9][10][11][12]: These algorithms minimize the circuit delay time of the specified design.…”