This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful functional decomposition algorithm. The impact of decomposition is enhanced by a preceding collapsing step. To decompose functions for small depth and area, we present an iterative, BDD-based variable partitioning procedure. The procedure optimizes the variable partition for each bound set size by iteratively exchanging variables between bound set and free set, and finally selects a good bound set size. Our decomposition algorithm extracts common subfunctions of multiple-output functions, and thus further reduces area and the maximum interconnect lengths. Experimental results show that our new algorithm produces circuits with significantly smaller depths than other performance-oriented mappers. This advantage also holds for the actual delays after placement and routing. r d Design Automation Conference@Permission to make digitalhard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission andlor a fee.
The growing popularity of look-up table (LUT)-based field programmable gate arrays (FPGA's) has renewed the interest in functional or Roth-Karp decomposition techniques. Functional decomposition is a powerful decomposition method that breaks a Boolean function into a set of subfunctions and a composition function. Little attention has so far been given to the problem of selecting good subfunctions after partitioning the input variables into the disjoint bound and free sets. Therefore, the extracted subfunctions usually depend on all bound variables. In this paper, 1 we present a novel decomposition algorithm that computes subfunctions with a minimal number of inputs. This reduces the number of LUT's and improves the usage of multiple-output SRAM cells. The algorithm iteratively computes subfunctions; in each iteration step it implicitly computes a set of possible subfunctions and finds a subfunction with minimal support. Moreover, our technique finds nondisjoint decompositions, and thus unifies disjoint and nondisjoint decomposition. The algorithm is very fast and yields substantial reductions of the number of LUT's and SRAM cells.
-This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful functional decomposition algorithm. The impact of decomposition is enhanced by a preceding collapsing step. To decompose functions for small depth and area, we present an iterative, BDD-based variable partitioning procedure. The procedure optimizes the variable partition for each bound set size by iteratively exchanging variables between bound set and free set, and finally selects a good bound set size. Our decomposition algorithm extracts common subfunctions of multiple-output functions, and thus further reduces area and the maximum interconnect lengths. Experimental results show that our new algorithm produces circuits with significantly smaller depths than other performance-oriented mappers. This advantage also holds for the actual delays after placement and routing.
Retiming is an optimization technique for synchronous circuits introduced by Leiserson and Saxe in 1983. Although powerful, re-timing is not very widely used because it does not handle in a satisfying way circuits whose registers have load enable, synchronous and asynchronous set/clear inputs. We propose an extension of re-timing whose basis is the characterization of registers into register classes. The new approach called multiple-class retiming handles circuits with an arbitrary number of register classes. We present results on a set of industrial FPGA designs showing the effectiveness and efficiency of multiple-class retiming.
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