Equivalence checking of scheduling with speculative code transformations in high-level synthesis

Lee, Myeong Soo; Shih,; Huang, Juinn-Dar; Jou,

doi:10.1109/aspdac.2011.5722241

Cited by 26 publications

(9 citation statements)

References 12 publications

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“…This method supports only uniform code motion techniques. The work reported in [10] improves the equivalence checking method of [4] to deal with code transformations employing speculation and global common sub-expression extraction. The enhanced method of [4] presented in [11] can handle both uniform and non-uniform code motions applied during the scheduling phase of HLS.…”

Section: Related Workmentioning

confidence: 99%

“…Many path-based approaches have been proposed for verification of HLS [3,4,7,[9][10][11][12][13][14][15], where each behaviour is represented by a finite state machine with datapath (FSMD) [16]. In general, path-based approaches decompose each FSMD into a finite set of finite paths and the equivalence of FSMDs is established by showing path level equivalence between two FSMDs.…”

Section: Introductionmentioning

confidence: 99%

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Counter‐example generation procedure for path‐based equivalence checkers

et al. 2019

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Path-based equivalence checkers (PBECs) have been successfully applied for verification of programmes from diverse domains and from various stages of high-level synthesis. In the case of non-equivalence, PBEC provides very little information which is not sufficient for further investigation of the two programmes being compared by some human expert. In this work, the authors show how a counter-trace (cTrace) can be generated in the case of non-equivalence reported by the PBEC. Using this cTrace, they also present a procedure to find suitable initialisation values for input variables which reveal the non-equivalence (i.e. counterexample) by using off-the-shelf satisfiability modulo theories (SMT) solvers. To aid the human expert, they also show that how they can visualise this cTrace in the control and data-flow graph of the programmes using the graph visualisation software-Graphviz. This counterexample and visual representation of the corresponding cTrace will be helpful in debugging the root cause of the non-equivalence. The experimental results are encouraging.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Counter‐example generation procedure for path‐based equivalence checkers

et al. 2019

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“…In this work, we have chosen the FSMD model to represent the programs since equivalence checking of FSMDs is a well studied problem and has found extensive application in translation validation of programs [5,7,8,4,2,3]. Specifically, FSMD based equivalence checking is first proposed in [5], which is later developed to handle uniform and nonuniform code motion based optimization techniques in [7,8,4].…”

Section: Introductionmentioning

confidence: 99%

“…Specifically, FSMD based equivalence checking is first proposed in [5], which is later developed to handle uniform and nonuniform code motion based optimization techniques in [7,8,4]. This method is general enough for checking equivalence of digital circuits as well [6].…”

Section: Introductionmentioning

confidence: 99%

A Scheme for Automated Evaluation of Programming Assignments using FSMD based Equivalence Checking

Sharma

Banerjee

Mandal

2014

Proceedings of the 6th IBM Collaborative Academia Research Exchange Conference (I-Care) on I-Care 2014

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This work presents an automated program evaluation scheme by leveraging the equivalence checking method of Finite State Machines with Data-path (FSMDs) which has found extensive application in translation validation of programs. In order to assess a student's program, it is compared with a model program supplied by the instructor. Besides reporting the error and providing feedback towards error correction, our method performs automated evaluation of programs which is particularly helpful in an environment where there is a large number of students, thus saving a lot of time for the instructor. Being automated, our scheme will ensure consistency in evaluation and ensure speedy evaluation.

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“…To solve the above problems, Chandan Karfa et al [13] and Lee et al [14]presented an equivalence checking method by comparing the path-pairs between cut-points in both FSMDs [15]. This technique can deal with path segments in designs, but the number of path segments is large and the comparison is inefficient without mapping information between the compared FSMDs.…”

Section: Introductionmentioning

confidence: 99%

Equivalence checking between SLM and RTL using machine learning techniques

2016

2016 17th International Symposium on Quality Electronic Design (ISQED)

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The growing complexity of modern digital design makes designers shift toward starting design exploration us ing high-level languages, and generating register transfer level (RTL) design from system level modeling (SLM) using high level synthesis or manual transformation. Unfortunately, this translation process is very complex and may introduce bugs into the generated design. In this paper, we propose a novel SLM and RTL sequential equivalence checking method. The proposed method bases on Finite state machines with datapath (FSMD) equivalence checking method. The proposed method recognizes the corresponding path-pairs of FSMDs using machine learning (ML) technique from all the paths. And then it compares the corresponding path-pairs by symbolic simulation. The advantage of our method is that it separates the corresponding path pairs from all the paths and avoids blind comparisons of path pairs. Our method can deal with greatly different SLM and RTL designs and dramatically reduce the complexity of the path-based FSMD equivalence checking problem. The promising experimental results show the efficiency and effectiveness of the proposed method.

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Equivalence checking of scheduling with speculative code transformations in high-level synthesis

Cited by 26 publications

References 12 publications

Counter‐example generation procedure for path‐based equivalence checkers

Counter‐example generation procedure for path‐based equivalence checkers

A Scheme for Automated Evaluation of Programming Assignments using FSMD based Equivalence Checking

Equivalence checking between SLM and RTL using machine learning techniques

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