A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses

Lin, Bu-Ching; Lee, Geeng-Wei; Huang, Juinn-Dar; Jou, Jing-Yang

doi:10.1109/aspdac.2007.357980

Cited by 16 publications

(5 citation statements)

References 4 publications

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“…Fixed priority is used in static algorithms. TDM [9] and Lottery [3,8] are two kinds of dynamic algorithm. Daisy chain is a hybrid algorithm [1,2,15,27].…”

Section: Arbitration Mechanismmentioning

confidence: 99%

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Hard real-time bus architecture and arbitration algorithm based on AMBA

Ding

2015

2015 International Conference on Information and Communications Technologies (ICT 2015)

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Real-time processors are growly used in embedded applications. Considering that the time cost in data transfer among devices is much more than the time used for computation and operation, it's important to design a high-speed real-time bus structure in real-time systems. This paper offers a deep investigation to the characteristics of real-time systems as well as the basic structure of real-time processors and real-time buses. We designed a high-speed and time-predictable bus architecture called RTBus, where high-performance AXI protocol is employed. To accurately calculate the bus access time for master devices, a two-level real-time bus arbitration algorithm, which adopts the warning-line judgment mechanism and simulated annealing algorithm, is proposed for the operation of the RTBus. Finally, it is proved that RTBus provides a good solution to the conflicts when sharing resources in real-time processors.

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“…Fixed priority is used in static algorithms. TDM [9] and Lottery [3,8] are two kinds of dynamic algorithm. Daisy chain is a hybrid algorithm [1,2,15,27].…”

Section: Arbitration Mechanismmentioning

confidence: 99%

“…There are four kinds of master devices. They are classified according to their tasks [9]: 1. D-NR: Tasks are under no time constraint, and they cannot be issued if there is a task unfinished.…”

Section: B Devicesmentioning

confidence: 99%

Hard real-time bus architecture and arbitration algorithm based on AMBA

Ding

2015

2015 International Conference on Information and Communications Technologies (ICT 2015)

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“…Several works have been proposed to improve the bandwidth and latency of the shared bus architecture by employing sophisticated arbitration schemes [16][17][18] and by physically segmenting the bus to enable concurrent communications [19,20]. Medardoni et al [21] analyzed the effect of the protocol, bridge design and traffic pattern on the hierarchical bus architecture and Drinic et al [22] proposed the automated design method for hierarchical bus architecture.…”

Section: Related Workmentioning

confidence: 99%

Design of On-Chip Crossbar Network Topology Using Chained Edge Partitioning

Jun

Chung

2010

The Computer Journal

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This paper proposes an efficient topology synthesis method for on-chip interconnection network based on crossbar switches. The efficiency of topology synthesis methods is often measured by two metrics-the quality of the synthesized topology and synthesis time. These two metrics are critically determined by the definition of the topology design space and the exploration method. Furthermore, an efficient representing method for the design space is required to tightly link the design space and the exploration method. Even though topology synthesis methods have actively been researched, most of the previous methods were not deep in thought for these factors. Unlike the previous methods, we propose a topology synthesis method with a careful consideration of these factors. Our method efficiently defines the design space by a technique called chained edge partitioning, in conjunction with a representing method for the points in the space, called enhanced restricted growth function. We also provide an exploration method which well incorporates with the aforementioned search space. To prove the effectiveness of our method, we compared our method with previous methods. The experimental results show that our method outperforms the compared methods by up to 49.8% and 104.6× in the quality of the synthesized topology and the synthesis time, respectively.

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“…It showed outstanding results for high bandwidth IPs with a short latency constraint, but it could not handle efficiently for low (high) bandwidth IPs with a short (long) latency constraint. The methods for real-time IPs are also proposed in [3] and [4]. However, their performance drastically decreases when the total requested bandwidth from the IPs reaches the system bandwidth.…”

Section: Previous Qos Arbitration Schemesmentioning

confidence: 99%

Jitter-Conscious Bus Arbitration Scheme for Real-Time Systems

Roh

Jun

Bang

et al. 2009

IEICE Trans. Fundamentals

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Jitter is the variation of latencies, when real-time Intellectual Properties (IPs) are accessing data from the data storages. It is a critical factor for such IPs from the Quality-of-Service (QoS) perspective. Jitter of a real-time IP can be measured by how frequently it experiences the underflows and overflows from its data queue in read mode and write mode, respectively. Such failures critically depend on the bus arbitration scheme which determines the bus acquisition order of IPs. The proposed idea allows IPs to inform the bus arbiter of the status of their data buffers when they assert bus requests. Such information helps the bus arbiter to determine the bus acquisition order while greatly reducing the jitter. The experimental results show that our method effectively eliminates the overflows and underflows of real-time IPs by dynamically preempting the jittercritical bus requests.

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A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses

Cited by 16 publications

References 4 publications

Hard real-time bus architecture and arbitration algorithm based on AMBA

Hard real-time bus architecture and arbitration algorithm based on AMBA

Design of On-Chip Crossbar Network Topology Using Chained Edge Partitioning

Jitter-Conscious Bus Arbitration Scheme for Real-Time Systems

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