Area Minimization Synthesis for Reconfigurable Single-Electron Transistor Arrays with Fabrication Constraints

Abstract

Power dissipation has become a pressing issue of concern in the designs of most electronic system as fabrication processes enter even deeper submicron regions. More specifically, leakage power plays a dominant role in system power dissipation. An emerging circuit design style, the reconfigurable single-electron transistor (SET) array, has been proposed for continuing Moore's Law due to its ultra-low leakage power consumption. Recently, several works have been proposed to address the issues related to automated synthesis for the reconfigurable SET array. Nevertheless, all of those existing approaches consider mandatory fabrication constraints of SET array merely in late synthesis stages. In this article, we propose a synthesis algorithm, featuring input-variable ordering and dynamic product term ordering, for area minimization. The fabrication constraints are taken into account at every synthesis stage of proposed flow to guarantee better synthesis outcomes. We also develop a simulated annealing-based postprocess to find a proper phase assignment of each input variable for further area reduction. Experimental results show that our new methodology can achieve up to 29% area reduction as compared to existing state-of-the-art techniques.

ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays

“…To evaluate the proposed method we compare it against two prior synthesis techniques [17] [20]. A set of experiments have been conducted for comparisons over a set of 21 test cases, which are selected from the MCNC benchmark suite [21] and IWLS benchmark suite [14].…”

“…Furthermore, the results of the complete proposed flow (first phase + second phase) are shown in the last part in Table 1. The synthesis technique for reconfigurable SET array proposed in [17] is used to generate the final mapping results.…”

“…After performing the actual SET mapping [17], the results demonstrate that our approach can reduce 49% and 38% of the SET array width as compared to [17] and [20], respectively. The results also show that the use of the number of one-paths as a metric is very effective for product term minimization in a reconfigurable SET synthesis flow.…”

“…The proposed algorithm consists of two phases, the first variable exploration for larger solution space as well as the next variable determination that can find a fairly good variable ordering within each solution space. The experimental results demonstrate that the proposed method achieves 55% and 44% reduction of the number of product terms as compared to [17] and [20], respectively. Besides, our approach can also reduce the mapped width of SET array by 49% and 38% as compared to [17] and [20], respectively.…”

“…Consequently, in our opinion, minimizing the width of the mapped SET array is more advantageous than minimizing the number of hexagons because it is obvious that the width can better estimate the area than the hexagon count. Another recent work proposed an area minimization synthesis flow for reconfigurable SET arrays, which takes two fabrication constraints into account in early stages [17]; it can achieve significant improvement as compared with other works.…”