In this paper, the properties of crosstalk on SiC planar MOSFET, SiC symmetrical double-trench MOSFET and SiC asymmetrical double-trench MOSFET is investigated on a half-bridge topology, to enable analysis of the impact of temperature, drain-source transition speed and gate resistance on the severity of the shoot-through current and induced gate voltage. The experimental measurements, performed on a wide range of temperatures and switching rates, show that the two selected symmetrical and asymmetrical double-trench MOSFETs exhibit higher induced gate voltage during crosstalk with the same external gate resistance compared with the planar SiC MOSFET, yielding a higher shoot-through current. Therefore, in continuous initiation of intentional crosstalk, the two doubletrench MOSFETs experience more temperature rise, especially for symmetrical one which leads the device to verge of failure within minutes while the temperature rise in other two devices is significantly lower. The different trends of shoot-through current with temperature on DUTs reveals that they are dominated by different mechanisms, i.e., influenced by threshold voltage and inversion layer carriers' mobility. A model is developed for prediction of shoot-through current during crosstalk which is validated for the 3 device structures. The comparison of the modelled results with the measurement proves its capability to predict the crosstalk behaviour.
In this paper, the reliability of planar, symmetrical, and asymmetrical SiC MOSFET is compared under repetitive short circuit shocks. Both static and dynamic parameters are tested after certain cycles to investigate the degradation pattern of the devices. It has been found out that the planar device has the highest reliability and is barely degraded for almost all parameters after 5000 cycles. The symmetrical device has the lowest reliability, which shows degradation after 50 cycles and ultimately fails after 141 cycles. The asymmetrical device shows significant degradation after 100 cycles and fails to turnon/off after 1000 cycles. For both symmetrical and asymmetrical devices, the degradation is directly linked to the damage of the gate oxide.
In this paper, the crosstalk-induced shoot-through current and induced gate voltage of SiC planar MOSFETs, SiC symmetrical double-trench MOSFETs and SiC asymmetrical double-trench MOSFETs is investigated on a half-bridge circuit to analyse the impact of temperature, drain-source voltage switching rate, gate resistance and load current level on crosstalk-induced properties of different SiC MOSFET structures. It shows that due to the smaller gate-source capacitance, the two double-trench MOSFETs exhibit higher induced gate voltage during crosstalk with the same external gate resistance, which together with the higher transconductance, yield higher shoot-through current than the planar MOSFET. Accordingly, their shoot-through current decreases with increasing of the load current while the planar MOSFET exhibits an opposite trend. The different trend of shoot-through current with temperature on DUTs reveals that the crosstalk in different device structures are dominated by different mechanisms, i.e. threshold voltage and channel mobility with the gate-source capacitance influencing the amplitude. Impact of bias temperature instability with positive and negative gate stressing is measured with a range of stress and recover periods at temperateness ranging between 25°C to 175°C. These measurements show that the peak shoot-through correlates with the threshold drift, though with less sensitivity for SiC symmetrical and asymmetrical double-trench MOSFETs compared with the planar SiC MOSFET where the inter-dependence is pronounced. A model is developed for the induced gate voltage and shoot-through current during crosstalk with channel current considered. The comparison of the model results with measurement confirms its capability to predict crosstalk in different MOSFET structures.
In this paper, dynamic switching performance at 1 st and 3 rd quadrant operation of Silicon and Silicon Carbide (SiC) symmetrical and asymmetrical double-trench, superjunction and planar power MOSFETs is analysed through a wide range of experimental measurements using compact modeling. The devices are evaluated on a high voltage clamped inductive switching test rig and switched at a range of switching rates at elevated junction temperatures. It is shown, experimentally, that in the 1 st quadrant, CoolSiC (SiC asymmetrical double-trench) MOSFET and SiC symmetrical double-trench MOSFET demonstrate more stable temperature coefficients. Silicon Superjunction MOSFETs exhibits the lowest turn-off switching rates due to the large input capacitance. The evaluated SiC Planar MOSFET also performs sub-optimally at turn-on switching due to its higher input capacitance and shows more temperature sensitivity due to its lower threshold voltage. In the 3 rd quadrant, the relatively larger reverse recovery charge of Silicon Superjunction MOSFET negatively impacts the turn-OFF transients compared with the SiC MOSFETs. It is also seen that among the SiC MOSFETs, the two double-trench MOSFET structures outperform the selected SiC planar MOSFET in terms of reverse recovery.
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