2022 IEEE Workshop on Wide Bandgap Power Devices and Applications in Europe (WiPDA Europe) 2022
DOI: 10.1109/wipdaeurope55971.2022.9936284
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Investigation of Repetitive Short Circuit Stress as a Degradation Metric in Symmetrical and Asymmetrical Double-Trench SiC Power MOSFETs

Abstract: In this paper, the reliability of planar, symmetrical, and asymmetrical SiC MOSFET is compared under repetitive short circuit shocks. Both static and dynamic parameters are tested after certain cycles to investigate the degradation pattern of the devices. It has been found out that the planar device has the highest reliability and is barely degraded for almost all parameters after 5000 cycles. The symmetrical device has the lowest reliability, which shows degradation after 50 cycles and ultimately fails after … Show more

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(3 citation statements)
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“…This phenomenon is because a more negative V gs can suppress the current density and lower the lattice temperature, proven by simulation results in [24], [66]. In [67], researchers discovered that after the device was turned-off in the short circuit event, the residual high temperature combined with negative V gs could provide enough energy for holes to inject and accumulate within the gate oxide, and mitigate the shift of parameters compared with the condition of the applied V gs of 0 V. In [58], similar phenomena was also reported, but different from the positive V th shift in most papers, radical negative drifts for both symmetrical and asymmetrical trench SiC MOSFETs were observed, as shown in Fig 21 . The reason behind was because of the negative V gs between short circuit intervals. The residual high temperature right after the short circuit caused energized holes to overcome the barrier and inject into the gate oxide, which not only counteracted but also outweighed the effect of injected electrons.…”
Section: B V Gsmentioning
confidence: 97%
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“…This phenomenon is because a more negative V gs can suppress the current density and lower the lattice temperature, proven by simulation results in [24], [66]. In [67], researchers discovered that after the device was turned-off in the short circuit event, the residual high temperature combined with negative V gs could provide enough energy for holes to inject and accumulate within the gate oxide, and mitigate the shift of parameters compared with the condition of the applied V gs of 0 V. In [58], similar phenomena was also reported, but different from the positive V th shift in most papers, radical negative drifts for both symmetrical and asymmetrical trench SiC MOSFETs were observed, as shown in Fig 21 . The reason behind was because of the negative V gs between short circuit intervals. The residual high temperature right after the short circuit caused energized holes to overcome the barrier and inject into the gate oxide, which not only counteracted but also outweighed the effect of injected electrons.…”
Section: B V Gsmentioning
confidence: 97%
“…The only reported degradation of dv/dt and di/dt under short circuit event was in [58]. However, the fluctuation was rather large.…”
Section: B Dynamic Parameters 1) Switching Timementioning
confidence: 98%
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