Analysis of the 1st and 3rd Quadrant Transients of Symmetrical and Asymmetrical Double-Trench SiC Power MOSFETs

Abstract

In this paper, dynamic switching performance at 1 st and 3 rd quadrant operation of Silicon and Silicon Carbide (SiC) symmetrical and asymmetrical double-trench, superjunction and planar power MOSFETs is analysed through a wide range of experimental measurements using compact modeling. The devices are evaluated on a high voltage clamped inductive switching test rig and switched at a range of switching rates at elevated junction temperatures. It is shown, experimentally, that in the 1 st quadrant, CoolSiC (SiC asymmetrical double-trench) MOSFET and SiC symmetrical double-trench MOSFET demonstrate more stable temperature coefficients. Silicon Superjunction MOSFETs exhibits the lowest turn-off switching rates due to the large input capacitance. The evaluated SiC Planar MOSFET also performs sub-optimally at turn-on switching due to its higher input capacitance and shows more temperature sensitivity due to its lower threshold voltage. In the 3 rd quadrant, the relatively larger reverse recovery charge of Silicon Superjunction MOSFET negatively impacts the turn-OFF transients compared with the SiC MOSFETs. It is also seen that among the SiC MOSFETs, the two double-trench MOSFET structures outperform the selected SiC planar MOSFET in terms of reverse recovery.

Investigation on threshold voltage instability under sweeping and DC gate bias stressing of SiC symmetrical and asymmetrical double-trench MOSFETs

“…Unlike Silicon MOSFET, SiC MOSFET is more sensitive to gate stressing because there is Carbon presented at the oxide-channel interface which are potential origins for the traps as well as its wide band-gap property makes traps of more energy level involved in the trapping/de-trapping of electrons [1,2]. Therefore, with the same oxide thickness, SiC MOSFET shows more threshold voltage shift than Silicon MOSFET [3,4]. The threshold voltage drift closely affects the circuit operation.…”

“…As the temperature increases to 175°C, such deviations by slowing down the sweeping speed is minimized. In theory, high temperature would cause more traps generated in the oxide layer [4] which yield more threshold voltage drift. However, the Constant Current method is the industrial approach to extract the threshold voltage that fits the ID to VGS equation of MOSFET in the linear region thus the mobility degradation with temperature rise would increase the required VGS to reach the current value as in VTH definition.…”

Electrothermal Power Cycling to Failure of Discrete Planar, Symmetrical Double-Trench and Asymmetrical Trench SiC MOSFETs

“…in transfer characteristics, are more prone to failure at repetitive short-circuit events than the fresh devices. However, these studied have primarily focused on conventional planar structured SiC MOSFETs, while there are newly developed trench-structured SiC MOSFETs with improved dynamic performance [18], [19] which lack similar studies. The cross-sectional schematics for planar structured power MOSFETs and the two trench power MOSFETs as symmetric & asymmetric are shown in Fig.…”

Crosstalk Induced Shoot-Through in BTI-Stressed Symmetrical & Asymmetrical Double-Trench SiC Power MOSFETs

“…The cross-sectional schematic drawing of the devices under test is shown in Fig. 1 as Planar, Symmetrical Double-trench and Asymmetrical Double-trench structures [14]. Compared with the planar MOSFET which is the conventional structure, symmetrical double-trench MOSFET is able to deliver lower on-resistance [15], [16] as it implements trenched source region to suppress the E field stress on the gate oxide [17].…”